參數(shù)資料
型號: DS1077Z-66
廠商: DALLAS SEMICONDUCTOR
元件分類: Clock Generator
英文描述: 66.666 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝: 0.150 INCH, SOIC-8
文件頁數(shù): 13/17頁
文件大?。?/td> 103K
代理商: DS1077Z-66
DS1077
5 of 17
Table 3
PDN0
(bit)
PDN1
(bit)
Shutdown Control
0
None*
0
1
CTRL1
1
0
CTRL0
1
CTRL0 or CTRL1
*CTRL0 performs a power down if SELO and ENO are both 0 (see Table 1)
Serial Data Input/Output (SDA) Input/Output pin for the 2-wire serial interface used for data transfer
Serial Clock Input (SCL) Input pin for the 2-wire serial interface used to synchronize data movement
on the serial interface.
REGISTER FUNCTIONS
The USER-PROGRAMMABLE REGISTERS can be programmed by the user to determine the mode
of operation(MUX) , operating frequency (DIV) and bus settings (BUS) . Details of how these registers
are programmed can be found in a later section; in this section the function of the registers are described.
The register setting are non-volatile, the values being stored automatically or as required in EEPROM
when the registers are programmed via the SDA and SCL pins.
MUX WORD
msb
lsb
msb
lsb
Name
*
PDN1
PDN0
SEL0
EN0
0M0
0M1
1M0
1M1
DIV1
-
Default seeting
0
1
0
x
first data byte
second data byte
*This bit must be set to “0” zero
DIV1 (bit)
This bit allows the output of the Prescaler P1 to be routed directly to the OUT1 pin (DIV1=1). The N
divider is
bypassed so the programmed value of
N is ignored. If DIV1=0 (default) the N divider
functions normally.
0M1, 0M0, 1M1, 1M0 (bits)
These bits set the prescalers P0 and P1 , to divide by 1, 2, 4, or 8. (Refer to Table 4)
Table 4
0M1
0M0
Prescaler
P0 Divisor
“M”
1M1
1M0
Prescaler
P1 Divisor
“M”
00
1**
00
1**
0
120
1
2
1
041
0
4
1
181
1
8
**Default Condition
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