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參數(shù)資料
| 型號： | DNCM00 |
| 廠商： | Lineage Power |
| 英文描述： | 10 Mbit/s Ethernet MAC ASIC Macrocell(10 M位/秒以太網(wǎng)MAC ASIC宏單元) |
| 中文描述： | 10 Mbit / s的以太網(wǎng)MAC ASIC的宏單元（位10米/秒以太網(wǎng)的MAC ASIC的宏單元） |
| 文件頁數(shù)： | 8/8頁 |
| 文件大小： | 73K |
| 代理商： | DNCM00 |
DNCM00
10 Mbit/s Ethernet MAC ASIC Macrocell
Advance Data Sheet
August 1996
For additional information, contact your Microelectronics Group Account Manager or the following:
U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P, Allentown, PA 18103
1-800-372-2447
, FAX 610-712-4106 (In CANADA:
1-800-553-2448
, FAX 610-712-4106)
ASIA PACIFIC:
Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 14 Science Park Drive, #03-02A/04 The Maxwell, Singapore 0511
Tel. (65) 778 8833
, FAX (65) 777 7495
JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600
, FAX (81) 3 5421 1700
For data requests in Europe:
MICROELECTRONICS GROUP DATALINE:
Tel. (44) 1734 324 299
, FAX (44) 1734 328 148
For technical inquiries in Europe:
CENTRAL EUROPE:
(49) 89 95086 0
(Munich), NORTHERN EUROPE:
(44) 1344 865 900
(Bracknell UK),
FRANCE:
(33) 1 47 67 47 67
(Paris), SOUTHERN EUROPE:
(39) 2 6601 1800
(Milan) or
(34) 1 807 1700
(Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information. ORCAis a trademark of Lucent Technologies Inc.
Copyright 1996 Lucent Technologies Inc.
All Rights Reserved
Printed in U.S.A.
August 1996
DS95-217ASIC
Printed On
Recycled Paper
4
Functional Description
(continued)
Receiver
The DNCM00 receiver consists of a state machine,
CRC generator, 64 Kbyte counter, and deserializer.
When the DNCM00 detects a low-to-high transition of
CRS and RXC is operating, it will send an RXSOP
signal to the host. The first 10 bits of preamble sensed
are ignored. After the first 10 bits of preamble, a SFD
sequence (10101011) will cause an RXSFD signal to
be sent. After RXSFD, the receiver will buffer each byte
of received data. After assembling the byte, a 1 RXC
RXBVLD signal will be sent to the host. The host has
eight RXC times to read the byte from the RXBYTE
register. When CRS falls, the receiver monitors the
result of CRC calculated on the last full byte. If CRS
falls on a byte boundary, the packet is either good or a
CRC error. If CRS falls on a nonbyte boundary, but the
last full byte received had a good CRC, its a good
packet with dribble bits. If CRS falls on a nonbyte
boundary and the last full byte CRC was bad, it is a
frame alignment error. The receiver will inform the host
of the end of packet by activating the RXEOP output for
one RXC.
Other receive statistics include RXJAB (packet with
>1518 bytes and a CRC or FAE), LONG (>1518 bytes
with good CRC), NUL (CRS high for indefinite time with
no SFD), and others that are described in the terminal
descriptions list. Receive statistics are valid from
RXEOP to the next RXSOP.
If the MFDUP input is low (half duplex), the receiver will
ignore any packets that start while TXE is high to avoid
buffering ones own transmitted packet. In order to
prevent glitches on CRS during a collision situation
from affecting the receiver, the receiver will ignore high-
to-low transitions of CRS if a packet reception is in
progress and the COL signal is present. If MFDUP is
high (full duplex), the receiver will ignore the COL
signal.
The DNCM00 does not have any physical address
registers or multicast address registers, nor does it
have any multicast address group detection logic. It
does have three outputs, PHYS, RXMULT and BRD,
one of which will activate after 6 bytes of data have
been received. PHYS means the first bit of data in the
packet was 0; RXMULT means the first bit was 1, and
at least 1 of the next 47 was 0; and BRD is a 48-bit
address of all 1s.
General Information
The DNCM00 is approximately 4100 gates without
scan logic. It exists as a fully synthesizable VerilogHDL
behavioral/state table description and can be easily
modified for specific customer requirements.
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