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參數(shù)資料
| 型號： | DNCM00 |
| 廠商： | Lineage Power |
| 英文描述： | 10 Mbit/s Ethernet MAC ASIC Macrocell(10 M位/秒以太網(wǎng)MAC ASIC宏單元) |
| 中文描述： | 10 Mbit / s的以太網(wǎng)MAC ASIC的宏單元（位10米/秒以太網(wǎng)的MAC ASIC的宏單元） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 73K |
| 代理商： | DNCM00 |
Advance Data Sheet
August 1996
DNCM00
10 Mbit/s Ethernet MAC ASIC Macrocell
Lucent Technologies Inc.
3
4
TXEOD
Transmit End of Data (Active-High).
activate one clock after the DMA receives a TXLD from the transmitter. The transmitter will load
and transmit that byte, and then transmit (inverted) CRC data according to the status of APND-
CRC and INVCRC.
Abort Transmit (Active-High).
Used to stop a transmission ungracefully. The transmitter will
immediately terminate a transmission if this input is set. Abort should be held high for two or
more TXC cycles. When a packet is aborted during preamble, the preamble is completed and the
APNDCRC and INVCRC inputs are followed. If ABORT is activated during transmission, trans-
mission immediately stops, and the APNDCRC and INVCRC inputs are followed.
Append CRC (Active-High).
Used to control if a 32-bit CRC polynomial is appended to the end
of a transmitted packet. If high, the CRC is appended.
Invert CRC (Active-High).
Used to invert the polarity of the 32-bit CRC polynomial. The normal
CRC is inverted prior to transmission. If INVCRC is high, the normal CRC will be reinverted
prior to sending, forcing a CRC error.
Test Mode (Active-High).
Used to modify the terminal count of transmit counters to speed up
testing. When TSTMODE is high, the counters are modified as follows:
Used to end a transmit operation normally. TXEOD should
ABORT
APNDCRC
INVCRC
TSTMODE
Counter
9.6
μ
s intergap
51.2
μ
s timer
DEFER timer
Transmit Data Byte.
edge of the TXLD input and is transmitted LSB first onto the medium.
Receive Clock.
10 MHz receive clock recovered from the receive data stream. RXC is assumed
not to be present when the medium is inactive. It is assumed that RXC will be delayed by up to
5 data bit times after CRS activates. RXC must be generated for 5 bit times after CRS goes low
to guarantee proper receiver operation. If RXC is delayed after CRS activates, it will cause inac-
curacies in some of the RX statistics (SHORT).
Receive Data.
RXD is strobed on the rising edge of RXC when CRS is active to assemble
receive data bytes.
Normal Count
96
512
24288
Modified Count
25
8
242
TXDB_[7:0]_
Transmit data. TXDB is loaded into the transmit shift register in the falling
RXC
RXD
Signal Information
(continued)
Table 1. Input Terminal Descriptions
(continued)
Input
Terminal
Description
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