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參數(shù)資料
| 型號： | DNCM00 |
| 廠商： | Lineage Power |
| 英文描述： | 10 Mbit/s Ethernet MAC ASIC Macrocell(10 M位/秒以太網(wǎng)MAC ASIC宏單元) |
| 中文描述： | 10 Mbit / s的以太網(wǎng)MAC ASIC的宏單元（位10米/秒以太網(wǎng)的MAC ASIC的宏單元） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 73K |
| 代理商： | DNCM00 |
6
Lucent Technologies Inc.
DNCM00
10 Mbit/s Ethernet MAC ASIC Macrocell
Advance Data Sheet
August 1996
4
Signal Information
(continued)
Netlist
Inputs: XC, RST, COL, MFDUP, RETRY_1_,
RETRY_0_, BSEL,PREAM_1_,
PREAM_0_, ISQE, DEFER, TXREQ,
TXEOD, ABORT, APNDCRC, INVCRC,
TSTMODE, TXDB_7_, TXDB_6_,
TXDB_5_, TXDB_4_, TXDB_3_,
TXDB_2_, TXDB_1_, TXDB_0_, RXC,
RXD, CRS
Outputs: TXACK, TXINPROG, TXD, TXLD, TXEOP,
LATE, EXDEF, DEF, COLDET, SCOL,
MCOL, CERR, LCRS, SQE, TXBYTE,
TXSOP, TXE, ABORTED,
RXCOUNT_15_, RXCOUNT_14_,
RXCOUNT_13_, RXCOUNT_12_,
RXCOUNT_11_, RXCOUNT_10_,
RXCOUNT_9_, RXCOUNT_8_,
RXCOUNT_7_, RXCOUNT_6_,
RXCOUNT_5_, RXCOUNT_4_,
RXCOUNT_3_, RXCOUNT_2_,
RXCOUNT_1_, RXCOUNT_0_,
RXBYTE_7_, RXBYTE_6_,
RXBYTE_5_, RXBYTE_4_,
RXBYTE_3_, RXBYTE_2_,
RXBYTE_1_, RXBYTE_0_, RXSOP,
RXEOP, RXBVLD, RXJAB, FAE, CRC,
RUNT, FRAG, LONG, PHYS, RXMULT,
BRD, SHORT, IFG, NUL
Functional Description
The DNCM00 consists of two main blocks, the trans-
mitter and receiver. A brief description of each block
follows.
Transmitter
The transmitter in the DNCM00 is made up of a state
machine, a preamble-jam counter block, a transmit
counters block, a 32-bit CRC generator, a 15-bit
deferral time-out counter, and a transmit serializer.
A transmit operation is initiated by the host activating
TXREQ. When TXREQ is recognized, the DNCM00 will
respond by activating TXACK. The DNCM00 will hold
TXACK active until TXREQ is dropped, until the trans-
mitter successfully sends the packet, or until transmit is
aborted because of excessive collisions, excessive
deferral, or a host initiated abort.
Transmission will begin if the 9.6
μ
s intergap timer has
expired. If the timer has reached 9.6
μ
s prior to TXREQ
packet, transmission will begin immediately. If TXREQ
is given before 6.4
μ
s of intergap and the DNCM00 was
the last station transmitting, the new packet will begin
transmission at 9.6
μ
s regardless of CRS. If the timer is
greater than 6.4
μ
s and CRS is high, the transmission
will defer until CRS deactivates, at which time the 9.6
μ
s timer will activate and transmission will start after
time-out.
Transmitter operation is controlled by a state machine
modelled after the one shown in Appendix B of the
1993 version of IEEE
*
802.3.
Immediately prior to starting preamble, the DNCM00
will send a 1 TXC signal, TXSOP, to the host. Another
DNCM00 output TXINPROG is valid while the
DNCM00 is actively transmitting.
Preamble is programmable by PREAM[1:0] to be 32,
40, 48 or 56 bits, and an 8-bit SFD (10101011) is
appended after preamble. The DNCM00 has no
address registers, so source and destination
addresses must be included in the byte stream sent by
the host. The DNCM00 does not provide automatic
frame padding.
*
IEEEis a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
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