參數(shù)資料
型號： DNC3X3425
英文描述： DNC3X3425 Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
中文描述： DNC3X3425四10/100 Mbits /秒以太網(wǎng)收發(fā)器宏單元
文件頁數(shù)： 9/32頁
文件大?。?/td> 757K
代理商： DNC3X3425
Advance Data Sheet
March 2000
DNC3X3425
Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
9
4
Signal Information
(continued)
Table 5. Clock and Reset Signals
* Double bonded with XLO.
Double bonded with RMCLK.
Signal
Type
Name/Description
EN_RMCK
I
Enable RMCLK
. When high, this signal selects RMCLK as the clock input.
This signal and EN_XTL cannot be high simultaneously.
Primary Input Clock.
The frequency of this clock can be either 125 MHz or
50 MHz. IN125 is used to indicate the appropriate frequency. This clock input
is used when EN_RMCK is high.
Input Clock Frequency Select
. When high, this signal will indicate that the
frequency of RMCLK is 125 MHz; else the clock frequency is 50 MHz.
Enable Crystal Input
. This signal, when high, will select the crystal input
(XLO) as the clock input. This signal and EN_RMCK cannot be high simulta-
neously.
Crystal Oscillator Input.
A 25 MHz crystal ± 25 ppm can be connected
across XLO and XHI. Alternately, a 25 MHz external CMOS oscillator can be
connected to this input. This clock input is used when EN_XTL is high.
Crystal Oscillator Output
. This pad does not have to be bonded out if crystal
is not used.
CLK25RAW.
25 MHz output clock.
RMCLKRAW.
Buffered version of the RMCLK. This is either 50 MHz or
125 MHz, depending on RMCLK frequency.
24 Hz Clock Output.
This is a 24 Hz output signal.
Full-Chip Reset.
Reset is active-high. The RST_BUSY signal will go low
when reset is complete. 10Base-T and 100Base-TX/-FX are in reset until
enabled and take 1.3 ms to come out of reset. The HWRESET pulse should
have a minimum width of 40 nS.
Power-On Reset.
If a powerup reset (PUR) cell from ASIC library is not used,
then tie this input low.
Reset Busy.
This signal indicates that the DNC3X3425 is in reset.
10Base-T in Reset.
This signal indicates that the 10 Mbits/s logic is in reset.
100Base-TX Reset.
This signal indicates that the 100 Mbits/s logic is in reset.
This pin, when high, powers up the 125 MHz PLL permanently, allowing
CK125P to be used for external logic at all times.
This pin, when high, powers up the 160 MHz PLL permanently, allowing
CK160 to be used for external logic at all times.
This pin is the feedback for CK125P Normally this will be connected to
CK125P or any external chip clock buffers for CK125P
This is a 160 MHz output clock; this will be available if 10Base-T is enabled or
BYPPD160 is high.
This is a 125 MHz output clock, which must be fed back to CK125_BUF. This
will be available when in 100Base-Tx mode or if BYPPD125 is high or if IN125
is high.
RMCLK
PADI*
IN125
I
EN_XTL
I
XLO
PADI
XHI
PADO
(optional)
O
O
CLK25RAW
RMCLKRAW
SLOWCLK[3:0]
HWRESET
O
I
POR
I
RST_BUSY[3:0]
RST_10_BUSY[3:0]
RST_TX_BUSY[3:0]
BYPPD125
O
O
O
I
BYPPD160
I
CK125_BUF
I
CK160
O
CK125P
O
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