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參數資料
| 型號： | DNC3X3425 |
| 英文描述： | DNC3X3425 Quad 10/100 Mbits/s Ethernet Transceiver Macrocell |
| 中文描述： | DNC3X3425四10/100 Mbits /秒以太網收發(fā)器宏單元 |
| 文件頁數： | 30/32頁 |
| 文件大小： | 757K |
| 代理商： | DNC3X3425 |
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30
DNC3X3425
Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
4
Register Information
(continued)
Table 29. MR31—Device-Specific Register 4 (Quick Status) Bit Descriptions
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
R = read, W = write.
Register/Bit
*
31.15 (ERROR)
Type
R
Description
Receiver Error.
When this bit is a 1, it indicates that a receive error has been
detected. This bit is valid in 100 Mbits/s only. This bit will remain set until cleared by
reading the register. Default is a 0.
False Carrier.
When bit [31.7] is set to 0 and this bit is a 1, it indicates that the carrier
detect state machine has found a false carrier. This bit is valid in 100 Mbits/s only. This
bit will remain set until cleared by reading the register. Default is 0.
Link Status Change.
When bit [31.7] is set to a 1, this bit is redefined to become the
LINK_STAT_CHANGE bit and goes high whenever there is a change in link status (bit
[31.11] changes state).
Remote Fault.
When this bit is a 1, it indicates a remote fault has been detected. This
bit will remain set until cleared by reading the register. Default is a 0.
Unlocked/Jabber.
If this bit is set when operating in 100 Mbits/s mode, it indicates
that the TX descrambler has lost lock. If this bit is set when operating in 10 Mbits/s
mode, it indicates a jabber condition has been detected. This bit will remain set until
cleared by reading the register.
Link Status.
When this bit is a 1, it indicates a valid link has been established. This bit
has a latching low function: a link failure will cause the bit to clear and stay cleared
until it has been read via the management interface.
Link Partner Pause.
When this bit is set to a 1, it indicates that the DNC3X3425
wishes to exchange flow control information.
Link Speed.
When this bit is set to a 1, it indicates that the link has negotiated to
100 Mbits/s. When this bit is a 0, it indicates that the link is operating at 10 Mbits/s.
Duplex Mode.
When this bit is set to a 1, it indicates that the link has negotiated to
full-duplex mode. When this bit is a 0, it indicates that the link has negotiated to half-
duplex mode.
Interrupt Configuration.
When this bit is set to a 0, it defines bit [31.14] to be the
RXERR_ST bit and the interrupt pin (MASK_STAT_INT) goes high whenever any of
bits [31.15:12] go high, or bit [31.11] goes low. When this bit is set high, it redefines
bit [31.14] to become the LINK_STAT_CHANGE bit, and the interrupt pin
(MASK_STAT_INT) goes high only when the link status changes (bit [31.14] goes
high). This bit defaults to 0.
Interrupt Mask.
When set high, no interrupt is generated by this channel under any
condition. When set low, interrupts are generated according to bit [31.7].
Lowest Autonegotiation State.
These 3 bits report the state of the lowest autonego-
tiation state reached since the last register read, in the priority order defined below:
000: Autonegotiation enable.
001: Transmit disable or ability detect.
010: Link status check.
011: Acknowledge detect.
100: Complete acknowledge.
101: FLP link good check.
110: Next page wait.
111: FLP link good.
Highest Autonegotiation State.
These 3 bits report the state of the highest autone-
gotiation state reached since the last register read, as defined above for bit [31.5:3].
31.14 (RXERR_ST)/
(LINK_STAT_CHANGE)
R
31.13 (REM_FLT)
R
31.12 (UNLOCKED)/
(JABBER)
R
31.11 (LSTAT_OK)
R
31.10 (PAUSE)
R
31.9 (SPEED100)
R
31.8 (FULL_DUP)
R
31.7 (INT_CONF)
R/W
31.6 (INT_MASK)
R/W
31.5:3
(LOW_AUTO__STATE)
R
31.2:0
(HI_AUTO_STATE)
R
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