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參數(shù)資料
| 型號(hào)： | DNC3X3425 |
| 英文描述： | DNC3X3425 Quad 10/100 Mbits/s Ethernet Transceiver Macrocell |
| 中文描述： | DNC3X3425四10/100 Mbits /秒以太網(wǎng)收發(fā)器宏單元 |
| 文件頁數(shù)： | 27/32頁 |
| 文件大?。?/td> | 757K |
| 代理商： | DNC3X3425 |
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Advance Data Sheet
March 2000
DNC3X3425
Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
27
4
Register Information
(continued)
Table 24. MR20—User-Defined Register
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
R = read, W = write.
Table 25. MR21—RXER Counter
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
R = read, W = write.
Table 26. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions
Bit
*
20.15:0
Type
R/W
Description
The data written into this user-defined register appears on the RG20_OUT[15:0]
bus.
Bit
*
21.0
Type
W
Description
This bit, when 0 puts this register in 16-bit counter mode. When 1, it puts this regis-
ter in 8-bit counter mode. This bit is reset to a 0 and cannot be read.
When in 16-bit counter mode, these maintain a count of RXERs. It is reset on a read
operation.
When in 8-bit counter mode, these maintain a count of RXERs. It is reset on a read
operation.
When in 8-bit mode, these contain a count of false carrier events (802.3 Section
27.3.1.5.1). It is reset on a read operaton.
When in 8-bit mode, these contain a count of disconnect events (Link Unstable 6,
802.3 Section 27.3.1.5.1). It is reset on a read operation.
21.15:0
R
21.7:0
R
21.11:8
R
21.15:12
R
Bit
*
Type
R
R/LH
Description
28.15:9 (UNUSED)
28.8 (BAD_FRM)
Unused.
Read as 0.
Bad Frame.
If this bit is a 1, it indicates a packet has been received without an
SFD. This bit is only valid in 10 Mbits/s mode.
This bit is latching high and will only clear after it has been read or the device has
been reset.
Code Violation.
When this bit is a 1, it indicates a Manchester code violation has
occurred. The error code will be output on the MRXD lines. Refer to Table 1 for a
detailed description of the MRXD pin error codes. This bit is only valid in
10 Mbits/s mode.
28.7 (CODE)
R/LH
This bit is latching high and will only clear after it has been read or the device has
been reset.
Autopolarity Status.
When register 30, bit 3 is set and this bit is a 1, it indicates
the DNC3X3425 has detected and corrected a polarity reversal on the twisted pair.
28.6 (APS)
R
If the APF_EN bit (register 30, bit 3) is set, the reversal will be corrected inside the
DNC3X3425. This bit is not valid in 100 Mbits/s operation.
Disconnect.
If this bit is a 1, it indicates a disconnect. This bit will latch high until
read. This bit is only valid in 100 Mbits/s mode.
Unlocked.
Indicates that the TX scrambler lost lock. This bit will latch high until
read. This bit is only valid in 100 Mbits/s mode.
RX Error Status.
Indicates a false carrier. This bit will latch high until read. This bit
is only valid in 100 Mbits/s mode.
Force Jam.
This bit will latch high until read. This bit is only valid in 100 Mbits/s
mode.
28.5 (DISCON)
R/LH
28.4 (UNLOCKED)
R/LH
28.3 (RXERR_ST)
R/LH
28.2 (FRC_JAM)
R/LH
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