參數(shù)資料
型號(hào)： DNC3X3425
英文描述： DNC3X3425 Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
中文描述： DNC3X3425四10/100 Mbits /秒以太網(wǎng)收發(fā)器宏單元
文件頁(yè)數(shù)： 12/32頁(yè)
文件大?。?/td> 757K
代理商： DNC3X3425
12
DNC3X3425
Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
4
Table 7. Testability Signals
LED_BLINK_EN
I
LED Blink Enable.
This pin, when low, disables blinking. When high, the LED
output will blink high for 42 ms and low for 42 ms whenever there is activity,
unless LED_STR_EN is high, in which case the blinking is 0.5 seconds high
and 0.5 seconds low. This signal is ORed with register 29, bit 11.
Organizationally Unique Identifier.
This can be programmed by the user,
upon instantiation of the macro.
Model Number.
6-bit model number of the device. This can be programmed
upon instantiation.
Revision Number.
The value of the present revision number. This can be
programmed upon instantiation.
Powerdown.
When high, this signal powers down the PHY and resets all
management registers.
Serial Select.
When this signal is high, it indicates 10 Mbit/s serial mode.
When SERIAL_SEL is low, the macro is in 100 Mbits/s or 10 Mbits/s parallel
mode.
Autonegotiation Done.
This signal goes high whenever autonegotiation has
completed. It will go low if autonegotiation has to restart.
Register 20 Access.
This bus provides access to the user-defined register.
A write to this register can be through MDIO.
OUI[24:3]
I
MODEL[5:0]
I
VERSION[3:0]
I
PWRDN[3:0]
I
SERIAL_SEL[3:0]
O
AUTODONE[3:0]
O
RG20_OUT[15:0]
[3:0]
O
Signal
Type
I
Description
TESTSEL[3:0]
Test Mode Select.
These pins enable the PHY to be in various test modes:
scan, analog, etc. Lucent requires access to these pins for manufacturing
testing. They should be held low for normal operation.
Test Mode Inputs.
These test inputs provide a high level of controllability to
the macrocell, either as scan inputs or as digital/analog test inputs/controls
depending on the test mode selected by TESTSEL[3:0].
TESTMDC
TESTTXD[3:0]
TESTTXER
TESTTXEN
TESTCRS[3:0]
TESTCOL[3:0]
TESTRXCK[3:0]
TESTTXCK[3:0]
TESTRXD[3:0][3:0]
TESTRXER[3:0]
TESTRXDV[3:0]
ATBOP
ATBON
ECLP
ECLN
TESTMDIN
TESTMDOUT
TESTMDHZ
I
O
Test Mode Outputs.
These test output pins provide observability in the form
of either scan outputs or digital/analog test outputs depending on the test
mode selected by TESTSEL[3:0]. The TESTRXD[3:0][3:0] and
TESTRXER[3:0] must be mapped to outputs during test. The other test
output should be mapped, if possible, to ease PHY debugging.
PADO
(optional)
Analog Test Output Pins
. These are used in Lucent test modes. They
should be connected to bond pads, but are not required to be connected to
package pins.
I
Test Mode MDIN, MDOUT, and MDHZ.
Input, output, and I/O control signals
from/to a bidirectional buffer.
O
O
Signal
Type
Description
Signal Information
(continued)
Table 6. Control/Status Signals
(continued)
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