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參數(shù)資料
| 型號： | DMC73C168 |
| 英文描述： | 8Bit Single Chip Microcontroller |
| 中文描述： | 8位單芯片微控制器 |
| 文件頁數(shù)： | 57/90頁 |
| 文件大?。?/td> | 742K |
| 代理商： | DMC73C168 |
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57
8Bit Single Chip Microcontroller
DMC73C167
cycle is completed, the I2C bus module will interrupt the CPU. But if the CPU masks
the interrupt, the following instruction can be used instead of the interrupt.
LOOP BTJ ZP %>80, MSTS, LOOP
Repeats LOOP unti l INT5_1F i s set
f) Clear INT5_1F bit and one byte read
MOVP %10000000, MSTS
MOVP %10001000, MCTL0
Cl ear bi t 7 of MSTS
(ACT/-
/RSRT
1
0
When the two instruction above are executed, the I2C bus will receive one byte of
data from the slave. After the interrupt or checking the INT5_1F flag, the valid
one byte of data can be taken by reading MDR.
MOVP MDATA, A
MOVP %10000000, MSTS
Stores read data i nto the A regi ster
Cl ear bi t 7 ( INT5_1F) of MSTS
g) Last one byte read
MOVP %10001100, MCTL0
After reading this byte, the I2C bus master should generate a stop condition. To do
this, it must send the message the "this is the last byte" by not generating the ACK
(nowledge) signal. This module does not generate the ACK signal by setting bit 2
(NACK) of MCTL0 to 1. After the interrupt or checking the INT5_1F flag, the
last one byte of data can be taken by reading MDATA.
MOVP MDATA, B
MOVP %10000000, MSTS
Stores read data i nto the B regi ster
Cl ear bi t 7 ( INT5_1F) of MSTS
h) Terminate transfer action (stop condition generation)
MOVP %10000001, MCTL0
After generating the stop condition, the INT5_1F will be set. If needed, the interrupt
can be masked or this bit may not be checked. However, to begin another transfer
on the I2C bus, this bit should be cleared first.
/LODUTY
/MDIR
/NACK
/BCM1
/BCM0)
0
1
0
0
0
(ACT/-
1
/RSRT
0
/LODUTY
/MDIR
/NACK
/BCM1
/BCM0)
0
0
0
0
1
￡￡á￡￡×￡￡
/BCM0)
(ACT/-
1
/RSRT
0
/LODUTY
/MDIR
/NACK
/BCM1
0
1
1
0
0
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