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參數(shù)資料
| 型號： | DMC73C168 |
| 英文描述： | 8Bit Single Chip Microcontroller |
| 中文描述： | 8位單芯片微控制器 |
| 文件頁數(shù)： | 36/90頁 |
| 文件大?。?/td> | 742K |
| 代理商： | DMC73C168 |
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36
8Bit Single Chip Microcontroller
DMC73C167
1) The port using as the interrupt input should be in the input mode. The output mode may
cause damage to the device. If the contents of the corresponding output port are changed
from 1 to 0, the interrupt flag will also set to 1.
2) If not used as the interrupt input, the corresponding interrupt enable should be disabled.
But even with the disabling of this interrupt enable, the interrupt flag will be changed.
The external interrupt timing is shown in Figure 5-6. The device needs additional circuitry
when INT1, INT3_0, and IN 5_0 are used as zero-cross detectors as shown in Figure 5-7.
The following conditions are needed :
1) The external interrupt level should be in the range from VCC +0.3V to VSS. The input
current must not exceed the specification.
2) Noise on the interrupt signal should be minimized because the noise debounce logic is not
implemented on chip. The function may fail due to continuous interrupts.
Caution :
It is possible that the INTn flag bits in the IOCNT registers could be unintentionally cleared by
using bit manipulation instructions (ANDP/ORP & XORP). To avoid these occurences, use
the MOVP and STA instructions when writing Data to IOCNT registers.
Figure 5-3. External Interrupt Timing
VCC
VSS
External
Input
VT+
VT-
Interrupt
Happen
Last
Happen
1
0
Interrupt
Execution
￡￡á￡￡×￡￡
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