參數(shù)資料
型號(hào)： DMC73C168
英文描述： 8Bit Single Chip Microcontroller
中文描述： 8位單芯片微控制器
文件頁(yè)數(shù)： 55/90頁(yè)
文件大?。?/td> 742K
代理商： DMC73C168
55
8Bit Single Chip Microcontroller
DMC73C167
Read two byte data from Slave B
Slave A address (0010001)
Slave B address (1010000)
a) Initialization of HDC/LDC, MCTL, and MDATA (Fosc.-4MHz)
MOVP
%>80, MCTL1
Master I2C hardware on;
power-on reset routi ne
H gh durati on w l l be 8us
Lowdurati on w l l be 8us
Cl ear MTS regi ster
MOVP
MOVP
MOVP
MOVP
%>F9, HDC
%>F9, LDC
%E0, MTS
%00100010, MDATA
Address out to Sl ave A
(wri te data to Sl ave A)
MOVP %10100001, MDATA
Address out to Sl ave B
(read data fromSl ave B)
b) Start condition generation and address transfer
For start condition, set BCM1 (=1), BCM0 (=0) of MCTL0. The next data transfer
cycle is for write, so clear bit 3 (MDIR). To enable the start action, set ACT bit
(bit 7 of MCTL0).
MOVP %10000010, MCTL0
After this instruction is executed, the I2C bus module will generate the start condition
and transfer 7 bits of address and 1 bit of direction information. After the address
cycle is completed, the I2C bus module will interrrupt the CPU. But if the CPU masks
the interrupt, the CPU must poll bit 7 (INT5_1F) of MSTS to check the address
transfer status.
c) Check status register (MSTS)
If the address transfer is completed successfully, the contents of MSTS will be 1001 ----
(INT5_1F/ALOST/BERR/BBUSY/-). Then the INT5_1F bit should be cleared
before the next transfer.
(ACT/-
/RSRT
/LODUTY
/MDIR
/NACK
/BCM1
/BCM0)
1
0
0
0
0
1
0
￡￡á￡￡×￡￡
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