參數(shù)資料
型號： DMC73C168
英文描述： 8Bit Single Chip Microcontroller
中文描述： 8位單芯片微控制器
文件頁數(shù)： 52/90頁
文件大?。?/td> 742K
代理商： DMC73C168
52
8Bit Single Chip Microcontroller
DMC73C167
Bit 6-0
Reserved.
These bit should always be zero.
Table 5-31. P50 0132h MSTS I2C Master Status
Bit
R
W
7
6
5
4
3
2
1
0
INT5_1F
INT5_1C
ALOST
CLOST
BERR
CBERR
BBUSY
-
Not Used
Not Used
Bit 7
INT5_1F. I2C Master Interrupt (INT5_1) Flag. (READ)
After every action is completed, this bit will be set and INT5_1 interrupt is requested
if it is enabled. This bit is set on the following condition and reset by writing 1 to
INT5_1C. In order to proceed to the next sequence, this bit must be cleared first by
writing 1 to the INT5_1C bit.
- When completed to output address data on I2C.
- 1 byte of data is transferred.
After generation of stop condition.
- When there is a I2C bus error or arbitration is lost.
INT5_1C. Clear I2C Master Interrupt (INT5_1) Flag. (WRITE)
0 = No effect.
1 = Clears I2C master interrupt (INT5_1) flag.
ALOST. Bus Arbitration Lost. (READ)
When a transfer is initiated while the I2C bus is busy, ALOST will be set, and the
transfer will be canceled. If the master loses arbitration during the addressing or
data transfer stages, it will stop the SDA line drive and set the ALOST bit.
0 = Normal operation.
1 = Bus arbitration is lost.
CLOST. Clear Arbitration lOst Flag. (WRITE)
0 = No effect.
1 = Clears arbitration lost flag.
BERR. Bus Error. (READ)
During a data transmission or address cycle, a no acknowledgement response will
set this bit.
0 = Normal operation.
1 = A bus error has occurred.
CBERR. Clear Bus Error Flag. (WRITE)
During a data transmission or address cycle, a no acknowledgement response will
0 = No effected.
1 = Clears bus error flag.
BBUSY. Bus Busy. (READ)
A start condition will set this bit, and a stop condition or master reset will clear it.
0 = I2C bus is idle.
1 = I2C bus is either busy internally or being used by another master device.
Bit 6
Bit 5
Bit 4
￡￡á￡￡×￡￡
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