參數(shù)資料
型號： DM9801A
文件頁數(shù)： 4/60頁
文件大小： 605K
代理商： DM9801A
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
4
Final
Version: DM9801A-DS-F01
May 30, 2001
Pin Description
Pin No.
Station Interface: Receive Data, Transmit Data and Management
85
TXD0
or
STXDAT
Serial Transmit Data Bit (GPSI Mode, INTFSEL = 1):
Transmit data input pin for serial data from the GPSI.
84
TXD1
or
BP1
SPROM Boot Page Select 1 (GPSI Mode, INTFSEL = 1):
Most significant bit of a 2-bit encoded select. The BP1 and BP0 inputs, select
one of four, 64-byte, SPROM pages to initialize the DM9801A management
registers. Master mode must be selected using the SMODE input.
83
TXD2
or
SI
Serial Data Input (GPSI Mode, INTFSEL = 1):
This is the serial data input pin to the DM9801A for the SPI bus. The SPI bus
operation is only valid if GPSI mode is selected.
82
TXD3
or
SMODE
Serial Mode Select (GPSI Mode, INTFSEL = 1):
This input pin selects the SPI buses mode of operation. The SPI bus modes
of operation are:
Master Mode (SMODE = 0)
Slave Mode (SMODE = 1)
The SPI bus operation is only valid if GPSI mode is selected.
86
TX_CLK
or
STDCLK
reference clock, to clock in nibble data from the MII when in MII interface
mode.
Serial Transmit Data Clock (GPSI Mode, INTFSEL = 1):
STDCLK is an output from the DM9801A. Used as the transmit reference
clock to clock in the STXDATA when in GPSI interface mode.
81
TX_EN
or
STXEN
when in MII interface mode.
Serial Transmit Enable (GPSI Mode, INTFSEL = 1):
Used to enable the transmit function of the GPSI when in GPSI interface
mode.
66
MDC
or
BP0
interface which is asynchronous to transmit and receive clocks. The
maximum clock rate is 2.5MHz.
SPROM Boot Page Select 0 (GPSI Mode, INTFSEL = 1):
Least significant bit of a 2-bit encoded select. The BP1 and BP0 inputs,
select one of four, 64-byte, SPROM pages to initialize the DM9801A
management registers. Master mode must be selected using the SMODE
input.
Pin Name
I/O
Description
I
Transmit Data Bit 0 (MII Mode, INTFSEL = 0):
Transmit data input pin, bit 0, for nibble data from the MII
I
Transmit Data Bit 1 (MII Mode, INTFSEL = 0):
Transmit data input pin, bit 1, for nibble data from the MII
I
Transmit Data Bit 2 (MII Mode, INTFSEL = 0):
Transmit data input pin, bit 2, for nibble data from the MII
I
Transmit Data Bit 3 (MII Mode, INTFSEL = 0):
Transmit data input pin, bit 3, for nibble data from the MII
O,Z
MII Transmit Clock (MII Mode, INTFSEL = 0):
TX_CLK is an output pin from the DM9801A. Used as the transmit data
I
MII Transmit Enable (MII Mode, INTFSEL = 0):
MII Transmit enable input, used to enable the transmit function of the MII
I
MII Serial Management Clock (MII Mode, INTFSEL = 0):
Synchronous clock to the MDIO management data input/output serial
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