參數(shù)資料
型號： DM9801A
文件頁數(shù)： 15/60頁
文件大?。?/td> 605K
代理商： DM9801A
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Final
Version: DM9801A-DS-F01
May 30, 2001
15
MII Interface Transmit and Receive Timing Diagram
(continued)
TX_CLK
RX_CLK
TX_EN
TXD
CRS
RXD
COL
RX_DV
0
0
0
0
COL may be asserted up to 120 us after CRS has been asserted. Once COL has been asserted, TX_CLK and RX_CLK run
at a period of 933.3 ns until COL and CRS are cleared. It can take up to about 600 us for CRS to clear.
RXPKT – COL Asserted
Figure 9
Management Interface - Read Frame Structure
32 "1"s
0
1
1
0
A4
A3
A0
R4
R3
R0
Z
0
Idle
Preamble
SFD
Op Code
PHY Address
Register Address
Turn Around
Data
Read
Idle
Write
MDC
MDIO Read
D15
D14
D1
D0
//
//
Management Interface - Write Frame Structure
32 "1"s
0
1
1
0
A4
A3
A0
R4
R3
R0
1
0
D15
D14
D1
D0
Idle
Preamble
SFD
Op Code
PHY Address
Register Address
Write
Turn Around
Data
Idle
MDC
MDIO Write
Figure 10
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