參數(shù)資料
型號: DM9801A
文件頁數(shù): 10/60頁
文件大?。?/td> 605K
代理商: DM9801A
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
10
Final
Version: DM9801A-DS-F01
May 30, 2001
Functional Description
The DM9801A is a single-chip Home Phoneline Network
transceiver .The DM9801A provides an IEEE 802.3u
subset Media Independent Interface (MII) or a pseudo-
standard General Purpose Serial Interface (GPSI).
The DM9801A enables home networking by allowing
Ethernet packets to be transported over common home
telephone wiring with no modifications, using Ethernet
CSMA/CD media access control procedures as defined in
the IEEE 802.3 standard. Figure 1 shows the major
functional blocks implemented in the DM9801A.
Figure 1
MII Interface
The DM9801A provides a subset Media Independent
Interface (MII) or a pseudo-standard General Purpose
Serial Interface (GPSI). The MII interface provides a
simple, easy way to implement connection between the
MAC Reconciliation layer and the DM9801A transceiver.
The MII is designed to make the differences between
various media transparent to the MAC sublayer.
The MII consists of a nibble wide receive data bus, a
nibble wide transmit data bus, and control signals to
facilitate data transfers between the PHY and the
Reconciliation layer.
TXD (transmit data) is a nibble (4 bits) of data that are
driven by the reconciliation sublayer synchronously with
respect to TX_CLK. For each TX_CLK period, which
TX_EN is asserted, TXD (3:0) are accepted for
transmission by the PHY.
TX_CLK (transmit clock) output to the MAC reconciliation
sublayer is a clock that provides the timing reference for
the transfer of the TX_EN, TXD, and TX_ER signals.
TX_EN (transmit enable) input from the MAC
reconciliation sublayer to indicate nibbles are being
presented on the MII for transmission on the physical
medium.
Muxed
GPSI or MII
Interface
RLL25
Encoder
RLL25
Decoder
Master PHY
Controller
Receiver
and
Digital PLL
Receiver AFE
HN Drivers
Transmit
Timing
Generator
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