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參數資料
| 型號： | DEM-ADS1201U |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | USING THE ADS1201 EVALUATION BOARD(ADS1201評估板的使用) |
| 中文描述： | 使用本ADS1201評估板（ADS1201評估板的使用） |
| 文件頁數： | 4/15頁 |
| 文件大?。?/td> | 741K |
| 代理商： | DEM-ADS1201U |
4
operate at the high modulator clock frequency
f
S
. The output
from the third integrator is decimated down by
N
and fed to
the input of the first differentiator. The three differentiators
operate at the low clock frequency of
f
S
/N
, where
N
is the
decimation ratio. Figures 16 and 17 shows the detailed
schematic of the
SINC
3
digital filter, as implemented in
Xilinx FPGA. The 40-bit filter output is latched onto the
output data register where it can be transferred into the PC
via the parallel port one byte at a time. Calibration and
scaling is performed in software once the raw data is loaded
into the PC memory.
Figure 6 shows the implementation of a single integrator in
Xilinx FPGA. The 40-bit wide incoming data is continu-
ously added to the previously accumulated result.
D
Q
CLK
+
Data In
Data Out
MCLK
40
FIGURE 6. Xilinx Integrator Implementation.
Figure 7 shows the implementation of a single differentiator.
The 40-bit wide incoming data is latched onto the D flip-flop
array while being subtracted from the previously latched
result.
D
Q
CLK
–
Data In
Data Out
MCLK
N
40
FIGURE 7. Xilinx Differentiator Implementation.
The 8-bit configuration register inside the FPGA is used to
program the modulator clock frequency (MCLK), which
runs the filter as well as the modulator. Decimation ratio can
be programmed by setting the appropriate bits of the two 8-
bit decimation registers designated as “dr_low” and “dr_hi”
in Figure 16. The ADS1201U evaluation software allows the
user to simply select from eight possible clock frequencies
and type in the desired decimation ratio. After this, the
output data rate is calculated and the appropriate values are
programmed into the configuration and decimation registers
inside the FPGA. The eight allowable modulator frequencies
are: 1M, 512, 256, 128, 64, 32, and 16kHz. The maximum
decimation ratio allowed is 8192. The minimum decimation
ratio is dependent on the selection of the modulator clock
frequency and is limited so the output data rate never
exceeds 1000Hz.
ADS1201 GAIN/OFFSET CALIBRATION
In an ideal ADC transfer function, if one connects the
midpoints of each quantization code with a straight line, the
line will pass through the origin with a 45
°
angle. Any
deviation from this ideal condition indicates the existence of
some type of error. If the line does not pass through the
origin, the converter has an offset error.
If the line is at a slope other than 45
°
, the converter has a
gain error. In addition to offset and gain errors, a typical
A/D converter will also have a complex nonlinearity profile.
In the ADS1201U, two pins are dedicated to control offset
and gain calibration, CAL
ENB
and GAIN/OFFSET. The user
normally performs offset and gain calibration after each
filter configuration. For offset calibration, pins CAL
ENB
and
GAIN/OFFSET are set to LOW and HIGH, respectively. As
a result, internal switches S
1
and S
2
are disconnected from
the device inputs (A
IN
+, A
IN
–), and S
3
and S
4
are connected
to reference voltage, V
REF
(Figure 8). With these conditions,
the output of the modulator is passed through the digital
filter. The filter output word is saved as the offset error. For
gain calibration, the internal switches, S
5
and S
6
, connect the
inputs to V
REF
and ground, respectively. Under these condi-
tions, the output of the filter is saved as the gain error. The
output values obtained from offset and gain calibration are
used to calculate a gain calibration coefficient
gc
as follows:
(9)
V
REF
= 2.5V
offset error = data when inputs are shorted
gain error = data when inputs are at V
REF
and ground
The normalized filter output is then calibrated as:
calibrated_output = (output – offset error) gc
where,
output
refers to uncalibrated output.
g
V
gain error
offset error
C
REF
=
(
)
Switch Cap
Σ
Modulator
S
1
S
3
S
2
S
5
S
4
S
6
V
REF
GND
V
REF
A
IN
+
A
IN
–
V
REF
FIGURE 8. ADS1201U Internal Connections for Gain/
Offset Calibration.
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