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參數(shù)資料
| 型號(hào)： | DEM-ADS1201U |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | USING THE ADS1201 EVALUATION BOARD(ADS1201評(píng)估板的使用) |
| 中文描述： | 使用本ADS1201評(píng)估板（ADS1201評(píng)估板的使用） |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 741K |
| 代理商： | DEM-ADS1201U |
1999 Burr-Brown Corporation
SBAA031
AB-146
Printed in U.S.A. May, 1999
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
USING THE ADS1201 EVALUATION BOARD
By Saeid Jannesari
FEATURES
G
EASY INSTALLATION AND USE
G
ON BOARD SINC
3
DIGITAL FILTER WITH PRO-
GRAMMABLE MODULATOR CLOCK AND DECI-
MATION RATIO
G
RETRIEVES FILTER OUTPUT DATA INTO PC
FOR ANALYSIS AND DISPLAY
G
PERFORMS FOURIER TRANSFORMS ON COL-
LECTED DATA
G
DISPLAYS DATA IN BOTH FREQUENCY AND
TIME DOMAIN
G
USER-FRIENDLY VISUAL BASIC GRAPHICAL
INTERFACE
This application bulletin provides information on the opera-
tion and usage of the ADS1201U evaluation fixture and
provides detailed description of the digital filter design
implemented into Xilinx XC4010E Field Programmable
Gate Array (FPGA). The latest information, along with the
FPGA files can be found on the Burr-Brown web site. The
ADS1201U evaluation board communicates to a PC via a bi-
directional parallel port. It is capable of collecting up to
8192 data words at a maximum data rate of 1000Hz. The
user interface software is written in Visual Basic and con-
trols the filter configuration and data retrieval, as well as
graphical display and analysis. Data can be displayed in time
and frequency domain. Optionally, retrieved data can be
saved to a file for transport to other graphical and math-
ematical software applications. In addition, a hard copy of
the displayed graphics in time or frequency domain can be
obtained. In this bulletin, a complete description of the
hardware and software features of the ADS1201U evalua-
tion kit will be given.
ADS1201U
Since the information in this bulletin concerns the
ADS1201U, the following is a brief description of the part.
ADS1201U is a single channel precision, wide dynamic
range, second-order Delta-Sigma (
Σ)
modulator operating
from a single +5V supply (see Figure 1 for device pinout).
The
Σ
modulator converts an analog signal into a 1-bit
digital data stream of ones and zeros. The ones density of the
output data stream is proportional to the input analog signal.
Oversampling and noise shaping are used to reduce the
quantization noise in the frequency band of interest. A
Σ
modulator can be used with a digital filter for wide dynamic
range A/D conversion of 24 bits of resolution or better.
Filtering the noise is the primary purpose of the digital filter.
Its secondary purpose is to convert the 1-bit data stream at
high sample rate into a higher bit data stream at lower rate
(decimation). The output data from the ADS1201U modula-
tor is read via the MOUT pin. The modulator outputs data at
the rising edge of MCLK with a short time delay, t
d
. It is
recommended to synchronize the reading of the output data
with the falling edge of MCLK (Figure 2). The collected
output of the modulator is then passed through a digital low-
pass filter and the resulting output word is decimated and
truncated to the desired data rate and effective resolution,
respectively. The combination of the
Σ
modulator and the
digital decimation filter forms a
Σ
A/D converter. For more
detailed information and specifications concerning the
ADS1201U modulator, refer to the ADS1201 data sheet.
t
d
M
OUT
M
CLK
FIGURE 2. ADS1201U Output Read Operation.
ADS1201
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AV
DD
REF
OUT
REF
IN
NIC
A
IN
P
A
IN
N
AGND
V
BIAS
REF
EN
MOUT
MCLK
DV
DD
DGND
CAL
GAIN/OFFSET
BIAS
EN
NIC: Not Internally Connected
FIGURE 1. ADS1201U Device Pinout.
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