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| 型號： | DEM-ADS1201U |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | USING THE ADS1201 EVALUATION BOARD(ADS1201評估板的使用) |
| 中文描述： | 使用本ADS1201評估板（ADS1201評估板的使用） |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 741K |
| 代理商： | DEM-ADS1201U |
3
OPA177GS
1k
1k
0.5k
1k
100
1k
1k
0.1
μ
F
2.5k
1k
J
1
OPA177GS
100
1k
–15V
OPA177GS
1k
JMP3
JMP4
A
IN
–
JMP1
JMP2
A
IN
+
0.1
μ
F
100pF
100pF
FIGURE 3. Analog Input Buffers.
Substituting
Z
by
e
–j
ω
T
,
the frequency response obtained is
as follows:
sin(
ω
(6)
Where
N
is the decimation ratio. It is easy to see from the
above frequency response that the location of the first notch
occurs at
f
S
/N
,
where
f
S
is the sampling frequency (MCLK)
and
N
is the decimation ratio. At the most basic level, the
digital filter simply performs a moving average of the
modulator output. Figure 4 shows the normalized frequency
response of the digital filter.
H j
N T
sin(
N
T
(
)
)
)
ω
=
3
0
–20
–40
–60
–80
–100
–120
–140
–160
0
1
2
3
4
5
6
Frequency (Hz)
G
NORMALIZED DIGITAL FILTER RESPONSE
FIGURE 4. Normalized Digital Filter Response.
The relationship betwen modulator clock (
f
S
), output data
rate and decimation ratio (
N
) is given by:
(7)
therefore, data rate can be used to place a specific notch
frequency in the digital filter response. For a
SINC
3
filter
response, the –3dB point is 0.262 times the data rate.
FILTER IMPLEMENTATION
For small decimation ratios and low clock rates, the linear
convolution of
x(n)
and
h(n)
in Equation 1 can be efficiently
implemented in software using the FFT algorithm. To do
this, one can make use of a property of DFT transform which
says convolution in time domain is identical to multiplica-
tion in frequency domain:
(8)
therefore, the DFTs of
x(n)
and
h(n)
are multiplied point by
point and the inverse DFT of the result is the desired linear
convolution. To make this technique work with the FFT
algorithm, one must make sure that the two sequences
x(n)
and
h(n)
have the same length and are powers of 2. For large
decimation ratios and high output data rates, a hardware
implementation of the
SINC
3
filter is more efficient. The
filter transfer function in Equation 5 can be implemented
using a series cascade of three integrators and three
differentiators as shown in Figure 5. The three integrators
y( )
h( ) ( )
x n
Y( )
H( ) ( )
=
=
Z
–1
i
Z
–1
i
Z
–1
i
Input
Z
–1
d
Z
–1
d
Z
–1
d
Output
f
S
N
FIGURE 5. SINC
3
Digital Filter Topology.
Data rate
f
N
S
=
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