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參數(shù)資料
| 型號： | DDX4100A |
| 文件頁數(shù)： | 3/27頁 |
| 文件大小： | 1737K |
| 代理商： | DDX4100A |
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DDX-4100
PIN FUNCTION
PIN
1
SDl_1/SDATA_
Table1
DESCRIPTION
NAME
TYPE
I
OUTPUT DRIVE
OUT
Input I
2
S Serial Data 1/AC97 Output Data
(I
S mode maps to L,R DDX)
Input I
2
S Serial Data 2/AC97 Input Data
(I
S mode maps to LS,RS DDX)
Input I
2
S Left/Right Clock/AC97 Synch.
Clock
Input I
2
S Serial Clock/AC97 Bit Clock
Digital Supply Voltage
Digital Ground
Global Reset (Active Low) This pin
is sensed only after 2 clock cycles
AC97 Enable/Disable (1=AC97;
0=I
2
S/SPDIF)
I
2
C Serial Data
I
2
C Serial Clock
Select Address (I2C/AC97)
Connect to ground or Leave open
2
SDl_2/SDATA_I
N
LRCKI/SYNC
I/O
2mA
3
I/O
2mA
4
5
6
7
BICKI/BIT_CLK
VDD_1
GND_1
RESET
I/O
I
4mA
CMOS Schmitt
In Pull-Up
CMOS Schmitt
In Pull-Down
2mA
CMOS In Pull-
Down
Analog IN
Analog In
Analog In
3mA
3mA
3mA
3mA
3mA
3mA
3mA
3mA
3mA
3mA
3mA
8
AC97_Mode
I
9
10
11
12
SDA
SCL
SA
N/C
I/O
I
I
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
VDD_2
XTI
XTO
GND_2
VCC
RXP
RXN
VSS
LFE_B
LFE_A
SRIGHT_B
SRIGHT_A
GND_3
VDD_3
RIGHT_B
RIGHT_A
LEFT_B
LEFT_A
GND_4
VDD_4
SLEFT_B
SLEFT_A
EAPD
I
O
I
I
O
O
O
O
O
O
O
O
O
O
O
Digital Supply Voltage
Crystal Oscillator Input (Clock Input)
Crystal Oscillator Output Do Not Load
Digital Ground
Analog Supply Voltage
S/PDIF receiver positive (L,R DDX)
S/PDIF receiver negative (L,R DDX)
Analog Ground
Pwm LFE (subwoofer) channel output (B)
Pwm LFE (subwoofer) channel output (A)
Pwm Surround right channel output (B)
Pwm Surround right channel output (A)
Digital Ground
Digital Supply Voltage
Pwm Right channel output (B)
Pwm Right channel output (A)
Pwm Left channel output (B)
Pwm Left channel output (A)
Digital Ground
Digital Supply Voltage
Pwm Surround Left channel output (B)
Pwm Surround Left channel output (A)
External Amplifier Power down (Active
Low)
I
2
S Left/Right Clock
I
2
S Serial Data 1 Output (L,R)
I
2
S Serial Data 2 Output (LS,RS)
I
2
S Serial Data 3 Output (C,SUB)
I
2
S Serial Clock
Digital Ground
Digital Supply Voltage
Clock Output (256fs or 512fs)
Device Power down (Active Low)
36
37
38
39
40
41
42
43
44
LRCKO
SDO_1
SDO_2
SDO_3
BICKO
GND_5
VDD_5
CKOUT
PWDN
I/O
O
O
O
I/O
O
I
2mA
2mA
2mA
2mA
4mA
8mA
CMOS In PullUp
3
Details and Specifications are subject to change without notice
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