參數(shù)資料
型號(hào): DDX4100A
文件頁數(shù): 26/27頁
文件大?。?/td> 1737K
代理商: DDX4100A
DDX-4100
BIT
D0
I/F
R
DSP
RST
1
NAME
SRC_Status
DESCRIPTION
When 0, the digital PLL in the SRC is
LOCKED. When 1 the digital PLL is OUT of
LOCK
When 1, the SPDIF interface is out of lock.
When 0 the interface is locked to the SPDIF
stream input.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Enable auto-muting if AC3 frame header found
Enable auto-muting if no CH1_STATUS bit
found
Reserved
Reserved
Reserved
Reserved
D1
R
1
SPDIF_Status
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
W
R
R
R
R
R
R
R
R/W
R/W
R
0
0
0
0
0
0
0
0
1
0
AC3_AMEN
CH1_AMEN
D12
D13
D14
D15
12.16 Coefficient Handling Registers (address 78h – 7Ah)
D15
D14
D13
D12
D11
C15
C14
C13
C12
C11
AD7 AD6 AD5 AD4 AD3 AD2 AD1
See Paragraph 10
12.17 Vendor ID Register (address 7Ch – 7Eh) (AC’97 only)
D15
D14
D13
D12
D11
D10
0
1
0
0
0
0
0
1
0
0
1
0
These registers are specific vendor identification for the DDX4100. Microsoft’s Plug and Play Vendor ID
code is “ALJ”. The REV7 0 field is for the Vendor Revision number. These are read only registers, any
request to one of these will be ignored.
R
R
R
W
R
R
R
R
0
0
0
0
D10
C10
D9
C9
D8
C8
AD0
D7
C7
R/W
D6
C6
D5
C5
D4
C4
D3
C3
C19 C18 C17
D2
C2
D1
C1
D0
C0
C16
D9
0
1
D8
1
0
D7
0
REV7
D6
1
REV6
D5
0
REV5
D4
0
REV4
D3
1
REV3
D2
1
REV2
D1
0
REV1
D0
0
REV0
26
Details and Specifications are subject to change without notice
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DDX4100ERRATA DDX4100 Errata January 17 2002
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