參數(shù)資料
型號： DDC101
英文描述： 20-BIT ANALOG-TO-DIGITAL CONVERTER
中文描述： 20位模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù)： 24/27頁
文件大?。?/td> 346K
代理商： DDC101
DDC101
24
FIGURE 24. Example of Basic DDC101 Circuit Connections.
Reading Data Output
Data from the previous conversion can be read any time after
the DATA VALID output is activated and before the end of
the next conversion. Data is held in an internal serial shift
register until the end of the next conversion. The data must
be completely read before the end of the next conversion or
it will be overwritten with new data.
Recommended Setup
The following Setup parameters are recommended, in gen-
eral, for use with the DDC101 with integration times of 1ms
or longer. Multiple integrations per conversion, where prac-
tical, will provide lowest noise as illustrated in the typical
performance curves.
Measurement Time Calculation
The time between “Final Data point Start” commands is the
Integration Time, T
. The Measurement Time, T
, is the
Integration time reduced by the Acquisition Time and by the
Oversampling Time, T
OS
.
T
MEAS
= T
INT
- T
ACQ
- T
OS
.
When CDS is used; T
, the oversampling time, is the time
required to collect a data point (M clock periods). Each
group of samples is averaged with the result at the midpoint
of each sample group. Therefore, with CDS, T
OS
= M clock
periods. This is shown in Figure 25.
Two calculations of the Measurement Time are shown
A Continuous Integration Cycle consists of the Acquisition
Time, Initial Data Point Collection, Tracking Interval, and
Final Data Point Collection. The user can select these
functions as illustrated in Table XV.
FUNCTION
RECOMMENDED
Acquisition Clocks, K
16
Oversamples, M
128
CDS
Enabled
USER
FUNCTION
CLOCK CYCLES
CONTROLLED
Acquisition Time, K
Initial Data Point
Samples, M
(1)
Tracking Interval
Final Data Point
Samples, M
(1)
1, 16, 32
Yes
1, 2, 4, 8, 16, 32,64, 128, 256
Variable
Yes
Yes
1, 2, 4, 8, 16, 32, 64, 128, 256
Yes
NOTE: (1) Will be the same in CDS mode, initial Data Point Samples = 0 in non-
CDS mode.
TABLE XV. Components of Integration Cycle.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
24-Lead SOIC
Top view
+5VDC
0.1μF
0.1μF
0.1μF
–5VDC
10μF
10μF
Analog Input
10μF
V
REF
Analog Common
Digital Common
Guard
DIGITAL GROUND
V
S
–
1k
25k
10μF
–2.5V
REF1004 –2.5
10
Reference
Bias
Resistor
Reference
Noise Filter
Reference Buffer Bypass
V
S
– , ANALOG
ANALOG COMMON
ANALOG INPUT
ANALOG COMMON
V
S
+, ANALOG
V
S
+, ANALOG
V
DD
+, DIGITAL
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