參數(shù)資料
型號： DC919A-F
廠商： Linear Technology
文件頁數(shù)： 29/32頁
文件大?。?/td> 0K
描述： BOARD DEMO 16BIT MSPS LTC2202
軟件下載： QuikEval II System
設(shè)計(jì)資源： DC919A Design Files
標(biāo)準(zhǔn)包裝： 1
系列： *
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LTC2203/LTC2202
6
22032fd
TIMING CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND, with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 25MHz (LTC2203), 10MHz (LTC2202),
input range = 2.5VP-P with differential drive (PGA = 0), unless otherwise
specied.
Note 5: Integral nonlinearity is dened as the deviation of a code from a
“best t straight line” to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code ickers between 0000 0000 0000 0000 and 1111 1111 1111
1111 in 2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
Note 9: Dynamic current from switched capacitor inputs is large compared
to DC leakage current, and will vary with sample rate.
Note 10: Leakage current will experience transient at power up. Keep
resistance < 1K Ω.
The
l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 4)
The
l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
LTC2203
TYP
MAX
MIN
LTC2202
TYP
MAX
UNITS
VDD
Analog Supply Voltage
l 3.135
3.3
3.465
3.135
3.3
3.465
V
PSHDN
Shutdown Power
SHDN = VDD, CLK = VDD
22
mW
OVDD
Output Supply Voltage
l
0.5
3.6
0.5
3.6
V
IVDD
Analog Supply Current
l
66
80
42
50
mA
PDIS
Power Dissipation
l
220
264
140
165
mW
POWER REQUIREMENTS
SYMBOL
PARAMETER
CONDITIONS
MIN
LTC2203
TYP
MAX
MIN
LTC2202
TYP
MAX
UNITS
fS
Sampling Frequency
l
1
25
1
10
MHz
tL
CLK Low Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
18.9
5
20
500
40
5
50
500
ns
tH
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
18.9
5
20
500
40
5
50
500
ns
tAP
Sample-and-Hold
Aperture Delay
0.9
ns
tD
CLK to DATA Delay
CL = 5pF (Note 7)
l
1.3
3.1
4.9
1.3
3.1
4.9
ns
tC
CLK to CLKOUT Delay
CL = 5pF (Note 7)
l
1.3
3.1
4.9
1.3
3.1
4.9
ns
tSKEW
DATA to CLKOUT Skew
CL = 5pF (Note 7)
l
–0.6
0
0.6
–0.6
0
0.6
ns
DATA Access Time
Bus Relinquish Time
CL = 5pF (Note 7)
(Note 7)
l
5
15
5
15
ns
Pipeline
Latency
7
Cycles
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