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| 型號： | DC919A-F |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DEMO 16BIT MSPS LTC2202 |
| 軟件下載： | QuikEval II System |
| 設(shè)計資源： | DC919A Design Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| 相關(guān)產(chǎn)品： | LTC2202IUK#TRPBF-ND - IC ADC 16-BIT 10MSPS 48-QFN LTC2202CUK#TRPBF-ND - IC ADC 16-BIT 10MSPS 48-QFN LTC2202IUK#PBF-ND - IC ADC 16-BIT 10MSPS 48-QFN LTC2202CUK#PBF-ND - IC ADC 16-BIT 10MSPS 48-QFN |
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LTC2203/LTC2202
23
22032fd
Data Format
The LTC2203/LTC2202 parallel digital output can be
selected for offset binary or 2’s complement format. The
format is selected with the MODE pin. This pin has a four
level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD.
An external resistor divider can be user to set the 1/3VDD
and 2/3VDD logic levels. Table 1 shows the logic states
for the MODE pin.
Table 1. MODE Pin Function
MODE
OUTPUT FORMAT
CLOCK DUTY
CYCLE STABILIZER
0(GND)
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overow Bit
An overow output bit (OF) indicates when the converter
is over-ranged or under-ranged. A logic high on the OF
pin indicates an overow or underow.
Output Clock
The ADC has a delayed version of the CLK input available
as a digital output. Both a noninverted version, CLKOUT+
and an inverted version CLKOUT– are provided. The
CLKOUT+/CLKOUT– can be used to synchronize the
converter data to the digital system. This is necesary
when using a sinusoidal clock. Data can be latched on the
rising edge of CLKOUT+ or the falling edge of CLKOUT–.
CLKOUT+ falls and CLKOUT– rises as the data outputs
are updated.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer in CMOS Mode. Each buffer is powered by OVDD
and OGND, isolated from the ADC power and ground. The
additional N-channel transistor in the output driver allows
operation down to low voltages. The internal resistor in
series with the output makes the output appear as 50Ω
to external circuitry and eliminates the need for external
damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2203/LTC2202 should drive a
minimum capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as a
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF. A resistor in
series with the output may be used but is not required
since the ADC has a series resistor of 43Ω on chip.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
22032 F10
OVDD
VDD
0.1μF
TYPICAL
DATA
OUTPUT
OGND
43Ω
OVDD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
LTC2203/LTC2202
Figure 9. Equivalent Circuit for a Digital Output Buffer
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