參數(shù)資料
型號(hào)： DC1011A-C
廠商： Linear Technology
文件頁數(shù)： 9/38頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2494
軟件下載： QuikEval System
設(shè)計(jì)資源： DC1011A Schematic
DC1011A Design Files
標(biāo)準(zhǔn)包裝： 1
系列： Easy Drive™, QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 15
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
已用 IC / 零件： LTC2494
已供物品： 板
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LTC2494
2494fd
applications inForMation
Bit 20 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 21 also pro-
vides underrange and overrange indication. If both Bit 21
and Bit 20 are HIGH, the differential input voltage is above
+FS. If both Bit 21 and Bit 20 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2494 Status Bits
Input Range
Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
MSB
VIN ≥ 0.5 VREF/Gain
0
1
0V ≤ VIN < 0.5 VREF/Gain
0
1/0
0
–0.5 VREF/Gain ≤ VIN < 0V
0
1
VIN < –0.5 VREF/Gain
0
Bits 20 to 4 are the 16-bit plus sign conversion result
MSB first.
Bit 4 is the least significant bit (LSB16).
Bits 3 to 0 are always LOW.
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 3). Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the first
rising edge of SCK. Bit 22 is shifted out of the device on
the first falling edge of SCK. The final data bit (Bit 0) is
shifted out on the on the falling edge of the 23rd SCK and
may be latched on the rising edge of the 24th SCK pulse.
On the falling edge of the 24th SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 23) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the IN+ and IN– pins remains
between –0.3V and VCC + 0.3V (absolute maximum op-
erating range) a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 VREF /Gain
to +FS = 0.5 VREF/Gain. For differential input voltages
greater than +FS, the conversion result is clamped to the
value corresponding to +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value –FS – 1LSB.
Figure 3. Channel Selection, Configuration Selection and Data Output Timing
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2494 F03
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
MSB
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
SIG
BIT 21
“0”
BIT 22
BIT 23
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
GS2
GS1
GS0
ODD
BIT 10 BIT 9
BIT 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
DON'T CARE
Hi-Z
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