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參數(shù)資料
| 型號： | DC1011A-C |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2494 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC1011A Schematic DC1011A Design Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2494 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2494IUHF#TRPBF-ND - IC ADC 16BIT W/PGA 38-QFN LTC2494CUHF#TRPBF-ND - IC ADC 16BIT W/PGA 38-QFN LTC2494CUHF#PBF-ND - IC ADC 16BIT W/PGA 38-QFN LTC2494IUHF#PBF-ND - IC ADC 16BIT W/PGA 38-QFN |
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LTC2494
2494fd
applications inForMation
CONVERTER OPERATION
Converter Operation Cycle
The LTC2494 is a multichannel, low power, delta-sigma,
analog-to-digital converter with an easy to use, 4-wire
interface and automatic differential input current cancella-
tion. Its operation is made up of four states (See Figure 2).
The converter’s operating cycle begins with the conver-
sion, followed by the sleep state, and ends with the data
input/output cycle. The 4-wire interface consists of serial
data output (SDO), serial clock (SCK), chip select (CS) and
serial data input (SDI). The interface, timing, operation
cycle and data output format is compatible with Linear’s
entire family of
DS converters.
Initially, at power-up, the LTC2494 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, if CS is HIGH, power
consumption is reduced by two orders of magnitude. The
part remains in the sleep state as long as CS is HIGH. The
conversionresultisheldindefinitelyinastaticshiftregister
while the part is in the sleep state.
Once CS is pulled LOW, the device powers up, exits the
sleep state, and enters the data input/output state. If CS
is brought HIGH before the first rising edge of SCK, the
device returns to the sleep state and the power is reduced.
If CS is brought HIGH after the first rising edge of SCK, the
data output cycle is aborted and a new conversion cycle
begins. The data output corresponds to the conversion
just completed. This result is shifted out on the serial data
output pin (SDO) under the control of the serial clock pin
(SCK). Data is updated on the falling edge of SCK allowing
theusertoreliablylatchdataontherisingedgeofSCK(see
Figure 3). The configuration data for the next conversion
is also loaded into the device at this time. Data is loaded
from the serial data input pin (SDI) on each rising edge
of SCK. The data input/output cycle is concluded once 24
bits are read out of the ADC or when CS is brought HIGH.
The device automatically initiates a new conversion and
the cycle repeats.
ThroughtimingcontroloftheCSandSCKpins,theLTC2494
offers several flexible modes of operation (internal or
external SCK and free-running conversion modes). These
various modes do not require programming and do not
disturbthecyclicoperationdescribedabove.Thesemodes
of operation are described in detail in the Serial Interface
Timing Modes section.
Ease of Use
The LTC2494 data output has no latency, filter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straightforward. Each conver-
sion, immediately following a newly selected input or
mode, is valid and accurate to the full specifications of
the device.
The LTC2494 automatically performs offset and full-scale
calibration every conversion cycle independent of the
input channel selected. This calibration is transparent to
the user and has no effect with the operation cycle previ-
ously described. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage variation, input channel
and temperature drift.
Easy Drive Input Current Cancellation
The LTC2494 combines a high precision, delta-sigma ADC
with an automatic, differential, input current cancellation
frontend.Aproprietaryfrontendpassivesamplingnetwork
Figure 2. LTC2494 State Transition Diagram
CONVERT
SLEEP
CHANNEL SELECT
CONFIGURATION SELECT
DATA OUTPUT
POWER UP
IN+= CH0, IN–= CH1
GAIN = 1, 50/60Hz,1X
2494 F02
CS = LOW
AND
SCK
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