參數資料
型號： DC1011A-C
廠商： Linear Technology
文件頁數： 18/38頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2494
軟件下載： QuikEval System
設計資源： DC1011A Schematic
DC1011A Design Files
標準包裝： 1
系列： Easy Drive™, QuikEval™
ADC 的數量： 1
位數： 16
采樣率（每秒）： 15
數據接口： MICROWIRE?，串行，SPI?
已用 IC / 零件： LTC2494
已供物品： 板
相關產品： LTC2494IUHF#TRPBF-ND - IC ADC 16BIT W/PGA 38-QFN
LTC2494CUHF#TRPBF-ND - IC ADC 16BIT W/PGA 38-QFN
LTC2494CUHF#PBF-ND - IC ADC 16BIT W/PGA 38-QFN
LTC2494IUHF#PBF-ND - IC ADC 16BIT W/PGA 38-QFN
LTC2494
2494fd
applications inForMation
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal (see Figure 8).
CS is permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is typically
concluded 4ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller. EOC = 1 while the conversion is in
progress and EOC = 0 once the conversion is complete.
On the falling edge of EOC, the conversion result is load-
ing into an internal static shift register. The output data
can now be shifted out the SDO pin under control of the
externally applied SCK signal. Data is updated on the fall-
ing edge of SCK. The input data is shifted into the device
through the SDI pin on the rising edge of SCK. On the
24th falling edge of SCK, SDO goes HIGH, indicating a
new conversion has begun. This data now serves as EOC
for the next conversion.
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 9).
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating or pulled HIGH
before the conclusion of the POR cycle and prior to each
fallingedgeofCS.Aninternalweakpull-upresistorisactive
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
Figure 9. Internal Serial Clock, Single Cycle Operation
10F
0.1F
2.7V TO 5.5V
Hi-Z
2494 F09
CS
SCK
(INTERNAL)
SDI
SDO
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
VCC
fO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28
35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2494
4-WIRE
SPI INTERFACE
EOC
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
BIT 21
BIT 22
BIT 23
BIT 10 BIT 9
BIT 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
GS2
GS1
GS0
ODD
DON'T CARE
MSB
SIG
“0”
OPTIONAL
10k
VCC
<tEOCTEST
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