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參數(shù)資料
| 型號： | DC1011A-A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 18/38頁 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2498 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC1011A Schematic DC1011A Design Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2498 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2498HUHF#TRPBF-ND - IC ADC 24BIT 16CH DELTA 38-QFN LTC2498HUHF#PBF-ND - IC ADC 24BIT 16CH DELTA 38-QFN LTC2498IUHF#TRPBF-ND - IC ADC 24BIT 16CH 38-QFN LTC2498CUHF#TRPBF-ND - IC ADC 24BIT 16CH 38-QFN LTC2498IUHF#PBF-ND - IC ADC 24BIT 16CH 38-QFN LTC2498CUHF#PBF-ND - IC ADC 24BIT 16CH 38-QFN |
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LTC2498
25
2498ff
applications inForMation
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH any time between the 1st rising edge and
the 32nd falling edge of SCK, see Figure 10. On the ris-
ing edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge
of SCK, the new input channel is loaded and valid for the
next conversion cycle. If CS goes HIGH between the 8th
falling edge and the 16th falling edge of SCK, the new
channel is still loaded, but the converter configuration
remains unchanged. In order to program both the input
channel and converter configuration, CS must go HIGH
after the 16th falling edge of SCK (at this point all data
has been shifted into the device).
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal, see Figure 11. In this case, CS is
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 4ms after VCC exceeds 2V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is floating or driven HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has finished and the device has entered
the sleep state. The device remains in the sleep state a
minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting and inputting data.
Figure 9. Internal Serial Clock, Single Cycle Operation
10F
0.1F
2.7V TO 5.5V
Hi-Z
2498 F09
CS
SCK
(INTERNAL)
SDI
SDO
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
VCC
fO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28
35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2498
4-WIRE
SPI INTERFACE
EOC
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
BIT 29
BIT 30
BIT 31
BIT 18 BIT 17
BIT 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
ODD
DON'T CARE
MSB
SIG
“0”
OPTIONAL
10k
VCC
<tEOCTEST
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