參數(shù)資料
型號(hào)： DC1011A-A
廠商： Linear Technology
文件頁(yè)數(shù)： 15/38頁(yè)
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2498
軟件下載： QuikEval System
設(shè)計(jì)資源： DC1011A Schematic
DC1011A Design Files
標(biāo)準(zhǔn)包裝： 1
系列： Easy Drive™, QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
已用 IC / 零件： LTC2498
已供物品： 板
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LTC2498
22
2498ff
External Serial Clock, Single Cycle Operation
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle, see Figure 6.
Theexternalserialclockmodeisselectedduringthepower-
up sequence and on each falling edge of CS. In order to
enter and remain in the external SCK mode of operation,
SCK must be driven LOW both at power-up and on each
CS falling edge. If SCK is HIGH on the falling edge of CS,
the device will switch to the internal SCK mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device re-
mains in the sleep state until the first rising edge of SCK
is seen while CS is LOW. The input data is then shifted
in via the SDI pin on each rising edge of SCK (including
the first rising edge). The channel selection and converter
configuration mode will be used for the following conver-
sion cycle. If the input channel or converter configuration
is changed during this I/O cycle, the new settings take
effect on the conversion cycle following the data input/
output cycle. The output data is shifted out the SDO pin
on each falling edge of SCK. This enables external circuitry
to latch the output on the rising edge of SCK. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. On the 32nd falling edge of SCK, the device
begins a new conversion and SDO goes HIGH (EOC = 1)
indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
applications inForMation
Figure 6. External Serial Clock, Single Cycle Operation
Hi-Z
2498 F06
Hi-Z
CS
SCK
(EXTERNAL)
SDI
SDO
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
VCC
fO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28
35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
10F
0.1F
LTC2498
2.7V TO 5.5V
4-WIRE
SPI INTERFACE
EOC
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
BIT 29
BIT 30
BIT 31
BIT 18 BIT 17
BIT 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
ODD
DON'T CARE
MSB
SIG
“0”
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