參數(shù)資料
型號: DAC1408D650HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 14-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
中文描述: 14-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, VQFN-64
文件頁數(shù): 53/98頁
文件大?。?/td> 2600K
代理商: DAC1408D650HN
DAC1408D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 26 November 2010
53 of 98
NXP Semiconductors
DAC1408D650
2
, 4
or 8
interpolating DAC with JESD204A
Table 62.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
RST_EXT_FCLK_TIME[7:0]
RST_EXT_FCLK register (address 04h) bit description
Access
R/W
Value
3Fh
Description
specifies extension time reset_fclk in f
clk
periods
Table 63.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
RST_EXT_DCLK_TIME[7:0]
RST_EXT_DCLK register (address 05h) bit description
Access
R/W
Value
20h
Description
specifies extension time reset_dclk (in dclk-periods)
Table 64.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
DCSMU_PREDIVIDER[7:0]
DCSMU_PREDIVCNT register (address 06h) bit description
Access
R/W
Value
1Eh
Description
value used by dcsmu predivider (at f
clk
)
Table 65.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
PLL_CHARGE_TIME[7:0]
PLL_CHARGETIME register (address 07h) bit description
Access
R/W
Value
32h
Description
PLL charge time
(at f
clk
/DCSMU_PREDIVIDER[7:0])
Table 66.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
PLL_RUNIN_TIME[7:0]
PLL_RUN_IN_TIME register (address 08h) bit description
Access
R/W
Value
32h
Description
PLL run in time (at f
clk
/DCSMU_PREDIVIDER[7:0])
Table 67.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
CA_RUNIN_TIME[7:0]
CA_RUN_IN_TIME register (address 09h) bit description
Access
R/W
Value
04h
Description
clock alignment run in time
(at f
clk
/DCSMU_PREDIVIDER[7:0])
Table 68.
Default settings are shown highlighted.
Bit
Symbol
3 to 0
SET_VCM[3:0]
SET_VCM_VOLTAGE register (address 16h) bit description
Access
R/W
Value
02h
Description
set lane common-mode voltage (see
Table 75
)
Table 69.
Default settings are shown highlighted.
Bit
Symbol
6 to 4
SET_SYNC_VCOM[2:0]
SET_SYNC register (address 17h) bit description
Access
R/W
Value
4h
Description
set synchronization transmitter common-mode level
(see
Table 76
)
set synchronization transmitter output level swing
(see
Table 77
)
2 to 0
SET_SYNC_LEVEL[2:0]
R/W
3h
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