參數(shù)資料
型號(hào): DAC1408D650HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 14-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
中文描述: 14-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, VQFN-64
文件頁(yè)數(shù): 43/98頁(yè)
文件大?。?/td> 2600K
代理商: DAC1408D650HN
DAC1408D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 26 November 2010
43 of 98
NXP Semiconductors
DAC1408D650
2
, 4
or 8
interpolating DAC with JESD204A
Table 30.
Default settings are shown highlighted.
Bit
Symbol
7
DAC_B_PD
DAC_B_CFG_1 register (address 0Ch) bit description
Access
R/W
Value
Description
DAC B power
on
off
DAC B Sleep mode
disabled
enabled
lower 6 bits for the DAC B offset
0
1
6
DAC_B_SLEEP
R/W
0
1
00h
5 to 0
DAC_B_OFFSET[5:0]
R/W
Table 31.
Bit
7 to 6
DAC_B_CFG_2 register (address 0Dh) bit description
Symbol
DAC_B_GAIN_COARSE[1:0]
Access
R/W
Value
1h
Description
least significant 2 bits for the DAC B gain setting for
coarse adjustment
the 6 bits for the DAC B gain setting for fine
adjustment
5 to 0
DAC_B_GAIN_FINE[5:0]
R/W
00h
Table 32.
Bit
7 to 6
DAC_B_CFG_3 register (address 0Eh) bit description
Symbol
DAC_B_GAIN_COARSE[3:2]
Access
R/W
Value
3h
Description
most significant 2 bits for the DAC B gain setting for
coarse adjustment
most significant 6 bits for the DAC B offset
5 to 0
DAC_B_OFFSET[11:6]
R/W
00h
Table 33.
Default settings are shown highlighted.
Bit
Symbol
1
MINUS_3DB
DAC_CFG register (address 0Fh) bit description
Access
R/W
Value
Description
NCO gain
unity
3 dB
noise shaper
disabled
enabled
0
1
0
NOISE_SHAPER
R/W
0
1
Table 34.
Default settings are shown highlighted.
Bit
Symbol
3 to 1
DAC_DIG_BIAS[2:0]
DAC_CURRENT_0 register (address 11h) bit description
Access
R/W
Value
3h
Description
bias current control (see
Table 46
)
Table 35.
Default settings are shown highlighted.
Bit
Symbol
3 to 1
DAC_MST_BIAS[2:0]
DAC_CURRENT_1 register (address 12h) bit description
Access
R/W
Value
3h
Description
bias current control (see
Table 46
)
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