參數(shù)資料
型號(hào): DAC1408D650HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 14-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
中文描述: 14-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, VQFN-64
文件頁(yè)數(shù): 47/98頁(yè)
文件大?。?/td> 2600K
代理商: DAC1408D650HN
DAC1408D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 26 November 2010
47 of 98
NXP Semiconductors
DAC1408D650
2
, 4
or 8
interpolating DAC with JESD204A
10.15.2.4
Page 1 bit definition detailed description
Please refer to
Table 47
for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 48.
Default settings are shown highlighted.
Bit
Symbol
7 to 6
MDS_EQCHECK[1:0]
MDS_MAIN register (address 00h) bit description
Access
R/W
Value
Description
lock mode
lock when (early = 1 and late = 1)
lock when (early = 1 and late = 1 and equal = 1)
lock when equal = 1
force_lock (equal-check = 1)
evaluation restart
no action
transition from 0 to 1 restarts evaluation_counter
NCO synchronization
no action
NCO synchronization enabled
synchronization reference
use lane 1 enable as reference for
synchronization
use lane 2/lane 3 enable as reference for
synchronization
maximum delay
maximum coarse delay is 16T_dclk
maximum coarse delay is 32T_dclk
MDS mode
slave mode
master mode
MDS function
disable MDS function
enable MDS function
00
01
10
11
5
MDS_RUN
R/W
0
1
4
MDS_NCO
R/W
0
1
3
MDS_SEL_LN23
R/W
0
1
2
MDS_32T_ENA
R/W
0
1
1
MDS_MASTER
R/W
0
1
0
MDS_ENA
R/W
0
1
Table 49.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
MDS_WIN_PERIOD_A[7:0]
MDS_WIN_PERIOD_A register (address 01h) bit description
Access
R/W
Value
80h
Description
determines MDS window LOW-time
Table 50.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
MDS_WIN_PERIOD_B[7:0]
MDS_WIN_PERIOD_B register (address 02h) bit description
Access
R/W
Value
40h
Description
determines MDS window HIGH-time
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