參數(shù)資料
型號: DAC1205D750HW
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC, up to 750 Msps; 2x 4x and 8x interpolating
中文描述: PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 12-BIT DAC, PQFP100
封裝: 14 X 14 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT638-1, HTQFP-100
文件頁數(shù): 30/42頁
文件大?。?/td> 352K
代理商: DAC1205D750HW
DAC1205D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 June 2011
30 of 42
NXP Semiconductors
DAC1205D750
Dual 12-bit DAC, up to 750 Msps; 4x and 8x interpolating
The settings applied to DAC_A_GAIN_FINE[5:0] (see
Table 20 “DAC_A_Cfg_2 register
(address 0Ah) bit description”
) and to DAC_B_GAIN_FINE[5:0] (see
Table 23
“DAC_B_Cfg_2 register (address 0Dh) bit description”
) define the fine variation of the
full-scale current (see
Table 40
).
Table 40.
Default settings are shown highlighted.
DAC_GAIN_FINE[5:0]
Decimal
32
...
0
...
31
The coding of the fine gain adjustment is two’s complement.
10.11 Digital offset adjustment
When the DAC1205D750 analog output is DC connected to the next stage, the digital
offset correction can be used to adjust the common-mode level at the output of the DAC.
It adds an offset at the end of the digital part, just before the DAC.
The settings applied to DAC_A_OFFSET[11:0] (see
Table 19 “DAC_A_Cfg_1 register
(address 09h) bit description”
and
Table 21 “DAC_A_Cfg_3 register (address 0Bh) bit
description”
) and to “DAC_B_OFFSET[11:0]” (see
Table 22 “DAC_B_Cfg_1 register
(address 0Ch) bit description”
and
Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit
description”
) define the range of variation of the digital offset (see
Table 41
).
13
14
15
1101
1110
1111
20.0
21.0
22.0
I
O(fs)
fine adjustment
Delta I
O(fs)
Two’s complement
10 0000
...
00 0000
...
01 1111
10.3 %
...
0
...
+10 %
Table 39.
Default settings are shown highlighted.
DAC_GAIN_COARSE[3:0]
Decimal
I
O(fs)
coarse adjustment
…continued
I
O(fs)
(mA)
Binary
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