參數(shù)資料
型號: DAC1205D750HW
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC, up to 750 Msps; 2x 4x and 8x interpolating
中文描述: PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 12-BIT DAC, PQFP100
封裝: 14 X 14 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT638-1, HTQFP-100
文件頁數(shù): 20/42頁
文件大?。?/td> 352K
代理商: DAC1205D750HW
DAC1205D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 June 2011
20 of 42
NXP Semiconductors
DAC1205D750
Dual 12-bit DAC, up to 750 Msps; 4x and 8x interpolating
Table 21.
Bit
7 to 6
Table 22.
Default settings are shown highlighted.
Bit
Symbol
7
DAC_B_PD
Table 23.
Bit
7 to 6
Table 24.
Bit
7 to 6
Table 25.
Default settings are shown highlighted.
Bit
Symbol
7 to 2 -
1
MINUS_3DB
DAC_A_Cfg_3 register (address 0Bh) bit description
Symbol
Access
DAC_A_GAIN_
COARSE[3:2]
DAC_A_
OFFSET[10:5]
Value
-
Description
most significant 2 bits for the DAC A gain
setting for coarse adjustment
most significant 6 bits for the DAC A offset
R/W
5 to 0
R/W
-
DAC_B_Cfg_1 register (address 0Ch) bit description
Access Value Description
R/W
0
1
R/W
0
1
R/W
-
DAC B power
on
off
DAC B Sleep mode
disabled
enabled
lower 5bits for the DAC B offset
6
DAC_B_SLEEP
5 to 1
DAC_B_OFFSET[4:0]
DAC_B_Cfg_2 register (address 0Dh) bit description
Symbol
Access Value Description
DAC_B_GAIN_
COARSE[1:0]
DAC_B_GAIN_
FINE[5:0]
R/W
-
less significant 2 bits for the DAC B gain setting
for coarse adjustment
the 6 bits for the DAC B gain setting for fine
adjustment
5 to 0
R/W
-
DAC_B_Cfg_3 register (address 0Eh) bit description
Symbol
Access
DAC_B_GAIN_
COARSE[3:2]
DAC_B_
OFFSET[10:5]
Value Description
-
most significant 2 bits for the DAC B gain
setting for coarse adjustment
-
most significant 6 bits for the DAC B offset
R/W
5 to 0
R/W
DAC_Cfg register (address 0Fh) bit description
Access
-
R/W
Value
-
Description
reserved
NCO gain
unity
3 dB
noise shaper
disabled
enabled
0
1
0
NOISE_SHPER
R/W
0
1
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