參數(shù)資料
型號： DAC1205D750HW
廠商： NXP SEMICONDUCTORS
元件分類： DAC
英文描述： Dual 12-bit DAC, up to 750 Msps; 2x 4x and 8x interpolating
中文描述： PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 12-BIT DAC, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT638-1, HTQFP-100
文件頁數(shù)： 10/42頁
文件大小： 352K
代理商： DAC1205D750HW
DAC1205D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 June 2011
10 of 42
NXP Semiconductors
DAC1205D750
Dual 12-bit DAC, up to 750 Msps; 4x and 8x interpolating
Clock inputs (CLKP and CLKN)
[2]
V
i
input voltage
CLKN
V
gpd
< 50 mV or
CLKP
V
gpd
< 50 mV
C
[3]
825
-
1575
mV
V
idth
input differential threshold
voltage
input resistance
input capacitance
C
[3]
100
-
+100
mV
R
i
C
i
Clock outputs (SYNCP and SYNCN)
V
o(cm)
common-mode output
voltage
V
O(dif)
differential output voltage
R
o
output resistance
Digital inputs (I0 to I11, Q0 to Q11)
V
IL
LOW-level input voltage
V
IH
HIGH-level input voltage
I
IL
LOW-level input current
I
IH
HIGH-level input current
Digital inputs (SDO, SDIO, SCLK, SCS_N and RESET_N)
V
IL
LOW-level input voltage
V
IH
HIGH-level input voltage
I
IL
LOW-level input current
I
IH
HIGH-level input current
Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN)
I
O(fs)
full-scale output current
D
D
-
-
10
0.5
-
-
M
pF
C
-
V
DDA(1V8)
0.3
1.2
80
-
V
C
D
-
-
-
-
V
C
C
I
I
GNDIO
1.6
-
-
-
-
60
80
0.8
V
DD(IO)(3V3)
V
-
-
V
V
IL
= 0.8 V
V
IH
= 2.3 V
A
A
C
C
I
I
GNDIO
2.3
-
-
-
-
20
20
1.0
V
DD(IO)(3V3)
V
-
-
V
V
IL
= 1.0 V
V
IH
= 2.3 V
nA
nA
register value = 00h
default register
compliance range
C
C
C
D
D
C
C
-
-
1.8
-
-
-
-
1.6
20
-
250
3
6
18
-
-
V
DDA(3V3)
-
-
-
-
mA
mA
V
k
pF
ppm/
C
ppm/
C
V
O
R
o
C
o
E
O
E
G
Reference voltage output (GAPOUT)
V
O(ref)
reference output voltage
V
O(ref)
reference output voltage
variation
I
O(ref)
reference output current
Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)
I
O(aux)
auxiliary output current
V
O(aux)
auxiliary output voltage
N
DAC(aux)mon
o
output voltage
output resistance
output capacitance
offset error variation
gain error variation
T
amb
= 25
C
I
C
1.2
-
1.25
117
1.30
-
V
ppm/
C
external voltage 1.25 V
D
-
40
-
A
differential outputs
compliance range
I
C
D
-
0
-
2.2
-
10
-
2
-
mA
V
bit
auxiliary DAC monotonicity guaranteed
Table 5.
V
DDA(1V8)
= V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
= V
DD(IO)(3V3)
= 3.3 V; AGND, DGND and GNDIO shorted together;
T
amb
=
40
C to +85
C; typical values measured at T
amb
= 25
C; R
L
= 50
differential; I
O(fs)
= 20 mA; PLL off unless
otherwise specified.
Symbol
Parameter
Conditions
Characteristics
…continued
Test
[1]
Min
Typ
Max
Unit
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