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參數(shù)資料
| 型號： | CYS25G01K100 |
| 英文描述： | Physical Layer Devices |
| 中文描述： | 物理層設(shè)備 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 212K |
| 代理商： | CYS25G01K100 |
CYS25G0101DX
Document #: 38-02009 Rev. *J
Page 9 of 15
AC Waveforms
AC Test Loads
AC Specifications
2.0V
0.8V
3.0V
GND
2.0V
0.8V
< 1 ns
< 1 ns
80%
20%
80%
20%
V
ICHH
3.0V
V
ICLL
V
th
= 1.4V
V
th
= 1.4V
< 150 ps
< 150 ps
80%
20%
80%
20%
V
IEHH
V
IELL
< 1.0 ns
< 1.0 ns
(a) LVTTL Input Test Waveform
V
IHH
(b) CML Input Test Waveform
(d) LVPECL Input Test Waveform
< 1 ns
< 1 ns
(c) HSTL Input Test Waveform
V
th
= 0.75V
V
th
= 0.75V
V
IHL
80%
20%
80%
20%
3.3V
OUTPUT
(a) TTL AC Test Load
(b)
CML AC Test Load
R1
R2
C
L
R
L
R1 = 330
R2 = 510
C
L
≤
10 p
F
(Includes fixture and
probe capacitance)
R
L
= 100
1.5V
OUTPUT
(c) HSTL AC Test Load
R1
R2
C
L
R1 = 100
R2 = 100
C
L
≤
7 pF
(Includes fixture and
probe capacitance)
OUT+
OUT
–
Table 6. AC Specifications
—
Parallel Interface
Parameter
t
TS
t
TXCLKI
t
TXCLKID
t
TXCLKIR
t
TXCLKIF
t
TXDS
t
TXDH
t
TOS
t
TXCLKO
t
TXCLKOD
t
TXCLKOR
t
TXCLKOF
t
RS
t
RXCLK
t
RXCLKD
t
RXCLKR
t
RXCLKF
t
RXDS
t
RXDH
t
RXPD
Description
Min.
154.5
6.38
40
0.3
0.3
1.5
0.5
154.5
6.38
43
0.3
0.3
154.5
6.38
43
0.3
0.3
2.2
2.2
–
1.0
Max.
156.5
6.47
60
1.5
1.5
Unit
MHz
ns
%
ns
ns
ns
ns
MHz
ns
%
ns
ns
MHz
ns
%
ns
ns
ns
ns
ns
TXCLKI Frequency (must be frequency coherent to REFCLK)
TXCLKI Period
TXCLKI Duty Cycle
TXCLKi Rise Time
TXCLKi Fall Time
Write Data Set-up to
↑
of TXCLKI
Write Data Hold from
↑
of TXCLKI
TXCLKO Frequency
TXCLKO Period
TXCLKO Duty Cycle
TXCLKO Rise Time
TXCLKO Fall Time
RXCLK Frequency
RXCLK Period
RXCLK Duty Cycle
RXCLK Rise Time
[6]
RXCLK Fall Time
[6]
Recovered Data Set-up with reference to
↑
of RXCLK
Recovered Data Hold with reference to
↑
of RXCLK
Valid Propagation Delay
156.5
6.47
57
1.5
1.5
156.5
6.47
57
1.5
1.5
1.0
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