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參數(shù)資料
| 型號： | CYS25G01K100 |
| 英文描述： | Physical Layer Devices |
| 中文描述： | 物理層設備 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 212K |
| 代理商： | CYS25G01K100 |
CYS25G0101DX
Document #: 38-02009 Rev. *J
Page 2 of 15
CDR PLL allows loop-timed operation of the transmit data path
while still meeting all Bellcore and ITU jitter requirements.
Multiple loopback and loop-through modes are available for
both diagnostic and normal operation. For systems containing
redundant SONET rings that are maintained in standby, the
CYS25G0101DX may also be dynamically powered down to
conserve system power.
16
TXD[15:0]
Input
Register
Shifter
Logic Block Diagram
TXCLKI
LOCKREF
TX PLL
X16
FIFO
IN
±
OUT
±
÷
16
(155.52 MHz)
LOOPTIME
TX Bit-Clock
REFCLK
±
DIAGLOOP
LINELOOP
LOOPA
16
Output
Register
RXD[15:0]
Shifter
RX CDR
PLL
÷
16
RXCLK
(155.52 MHz)
Recovered
Bit-Clock
Retimed
Data
(155.52 MHz)
Lock-to-Data/
Clock Control
Logic
Lock-to-Ref
LFI
SD
FIFO_ERR
TXCLKO
FIFO_RST
RESET
PWRDN
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