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參數(shù)資料
| 型號(hào)： | CYS25G01K100 |
| 英文描述： | Physical Layer Devices |
| 中文描述： | 物理層設(shè)備 |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 212K |
| 代理商： | CYS25G01K100 |
CYS25G0101DX
Document #: 38-02009 Rev. *J
Page 15 of 15
Document History Page
Document Title: CYS25G0101DX SONET OC-48 Transceiver
Document Number: 38-02009
REV.
**
*A
*B
ECN NO.
105847
108024
111834
Issue Date
03/22/01
06/20/01
12/18/01
Orig. of
Change
SZV
AMV
CGX
Description of Change
Change from Spec number: 38-00894 to 38-02009.
Changed Marketing part number.
Updated power specification in features and DC specs section. Changed
pinout to be compatible with CYS25G0102DX in pin diagram and descrip-
tions. Verbiage added or changed for clarity in pin descriptions section.
Changed input sensitivity in Receive Data Path section, page 6. RXCLK rise
time corrected to 0.3 nSec min. CML and LVPECL input waveforms updated
in test load and waveform section. Diagrams replaced for clarity Figures 1-10.
Added two Refclock diagrams Figures 9 and 10.
Updated temperature range, static discharge voltage, and max total RMS
jitter.
Updated the single ended swing and differential swing voltage for Receiver
CML compatible inputs. Created a separate table showing peak to peak and
RMS jitter for both TX PLL and RX PLL
.
Added Industrial temperature spec to pages 8, 11, and 15.
Added differential waveform definition.
Added BGA pinout and package information.
Changed LVTTL V
IHT
min. from 2.0 to 2.1 volts.
Added phase noise limits data.
Removed BGA pinout and package information.
Removed references to CYS25G0102DX.
Removed
“
Preliminary
”
from data-sheet
Add power up requirements to Maximum Ratings information
Revised power up requirements
*C
112712
02/06/02
TME
*D
113791
04/24/02
CGX
*E
*F
115940
117906
05/22/02
09/06/02
TME
CGX
*G
119267
10/17/02
CGX
*H
*I
*J
121019
122319
124438
11/06/02
12/30/02
02/13/03
CGX
RBI
WAI
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