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參數(shù)資料
| 型號： | CYS25G01K100 |
| 英文描述： | Physical Layer Devices |
| 中文描述： | 物理層設(shè)備 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大小： | 212K |
| 代理商： | CYS25G01K100 |
CYS25G0101DX
Document #: 38-02009 Rev. *J
Page 10 of 15
Notes:
6.
7.
8.
9.
10. The RMS and P-to-P jitter values are measured using a 12-KHz to 20-MHz SONET filter.
°
C.
11.
This device passes the Bellcore specification from -10
°
C to 85
°
C.
RXCLk rise time and fall times are measured at the 20 to 80 percentile region of the rising and falling edge of the clock signal.
The 155.52 MHz Reference Clock Phase Noise Limits for the CYS25G0101DX are illustrated in
Figure 5
.
+20 ppm is required to meet the SONET output frequency specification.
Table 7. AC Specifications
—
REFCLK
[7]
Parameter
t
REF
t
REFP
t
REFD
t
REFT
t
REFR
t
REFF
Description
Min.
154.5
6.38
35
–
100
0.3
0.3
Max.
156.5
6.47
65
+100
1.5
1.5
Unit
MHz
ns
%
ppm
ns
ns
REFCLK Input Frequency
REFCLK Period
REFCLK Duty Cycle
REFCLK Frequency Tolerance
—
(relative to received serial data)
[8]
REFCLK Rise Time
REFCLK Fall Time
Table 8. AC Specifications
–
CML Serial Outputs
Parameter
t
RISE
t
FALL
Description
Min.
60
60
Typical
Max.
170
170
Unit
ps
ps
CML Output Rise Time (20
–
80%, 100
balanced load)
CML Output Fall Time (80
–
20%, 100
balanced load)
Table 9. Jitter Specifications
Parameter
t
TJ-TXPLL
Description
Min.
Typical
[10]
Max.
[10]
0.03
0.007
0.035
0.008
Unit
UI
UI
UI
UI
Total Output Jitter for TX PLL (p-p)
[9]
Total Output Jitter for TX PLL (rms)
[9, 11]
Total Output Jitter for RX CDR PLL (p-p)
[9]
Total Output Jitter for RX CDR PLL (rms)
[9, 11]
0.04
0.008
0.05
0.01
t
TJ-RXPLL
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