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參數(shù)資料
| 型號： | CYM26KAH24AV33 |
| 英文描述： | Memory |
| 中文描述： | 內(nèi)存 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 161K |
| 代理商： | CYM26KAH24AV33 |
PRELIMINARY
CYM26KAH24AV33
Document #: 38-05324 Rev. **
Page 6 of 8
Ordering Information
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
Write Cycle No. 3 (WE Controlled, OE LOW)
Switching Waveforms
(continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
CE
ADDRESS
WE
DATA I/O
OE
Note 14
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
ADDRESS
WE
DATA I/O
Note 14
Speed (ns)
10
10
12
12
Ordering Code
Package Name
BG119
BG119
BG119
BG119
Package Type
119-Ball BGA
119-Ball BGA
119-Ball BGA
119-Ball BGA
Operating
Range
Commercial
Industrial
Commercial
Industrial
CYM26KAH24AV33-10BGC
CYM26KAH24AV33-10BGI
CYM26KAH24AV33-12BGC
CYM26KAH24AV33-12BGI
Note:
14. During this period the I/Os are in the output state and input signals should not be applied.
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