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參數(shù)資料
| 型號： | CYM26KAH24AV33 |
| 英文描述： | Memory |
| 中文描述： | 內(nèi)存 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 161K |
| 代理商： | CYM26KAH24AV33 |
PRELIMINARY
256K x 24 Static RAM Module
CYM26KAH24AV33
Cypress Semiconductor Corporation
Document #: 38-05324 Rev. **
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 17, 2003
Features
High-density 6-Megabit SRAM Module
High-speed CMOS SRAMs
—t
AA
= 10 ns
Single 3.3V power supply
Low active power(648 W at 10 ns)
TTL-compatible Inputs and Outputs
Available in standard 119-ball BGA
Functional Description
The CYM26KAH24AV33 is a 3.3V high-performance
6-Megabit static RAM organized as a 256K words by 24 bits.
This module is constructed from two SRAM dies mounted on
a multilayer laminate substrate combined to form a 24-bit
SRAM.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data from I/O pins
(I/O
0
through I/O
23
), is written into the location specified on the
address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. Then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
23
. See
the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O
0
through I/O
23
) are placed in a
high-impedance state when the device is deselected
(CEHIGH), and the outputs are disabled (OE HIGH), or during
a Write operation (CE LOW, and WE LOW).
The CYM26KAH24AV33 is available in a standard 119 BGA.
Selection Guide
-10
10
180
200
20
-12
12
170
190
20
Unit
ns
mA
mA
mA
Maximum Access Time
Maximum Operating Current
Commercial
Industrial
Commercial
Industrial
Maximum Standby Current
Functional Block Diagram
A[17:0]
WE/
OE/
CE/
I/O
0-23
I/O
0-11
I/O
12-23
I/O
0-11
I/O
12-23
CE0/
WE0/
OE0/
A[17:0]
A[17:0]
CE1/
WE1/
OE1/
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