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參數(shù)資料
| 型號： | CYM26KAH24AV33 |
| 英文描述： | Memory |
| 中文描述： | 內存 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 161K |
| 代理商： | CYM26KAH24AV33 |
PRELIMINARY
CYM26KAH24AV33
Document #: 38-05324 Rev. **
Page 5 of 8
Read Cycle No. 2 (OE Controlled)
[10, 11]
Write Cycle No. 1 (CE Controlled)
[12, 13]
Notes:
10. WE is HIGH for read cycle.
11.
Address valid prior to or coincident with CE transition LOW.
12. Data I/O is high impedance if OE = V
.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Switching Waveforms
(continued)
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
I
CC
I
SB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
CURRENT
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
ADDRESS
WE
DATA I/O
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