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參數(shù)資料
| 型號： | CYM26KAH24AV33 |
| 英文描述： | Memory |
| 中文描述： | 內(nèi)存 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 161K |
| 代理商： | CYM26KAH24AV33 |
PRELIMINARY
CYM26KAH24AV33
Document #: 38-05324 Rev. **
Page 4 of 8
AC Switching Characteristics
[3]
Over the Operating Range
Parameter
Read Cycle
Description
-10
-12
Unit
Min.
Max.
Min.
Max.
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[6, 7]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE active to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[4, 5]
CE active to Low Z
[5]
CE inactive to High Z
[4, 5]
CE active to Power-Up
CE inactive to Power-Down
10
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
12
3
3
10
5
12
6
0
0
5
6
3
3
5
6
0
0
10
12
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CE active to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[5]
WE LOW to High Z
[4, 5]
10
7
7
0
0
7
5
0
3
12
8
8
0
0
8
6
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
5
Switching Waveforms
Read Cycle No. 1
[8, 9]
Notes:
3.
4.
Tested initially and after any design or process changes that may affect these parameters.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
.
t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Device is continuously selected. OE, CE = V
IL
.
5.
6.
7.
8.
9.
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
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