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參數(shù)資料
| 型號： | CY8C42123-24SXIT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PDSO8 |
| 封裝： | 0.150 INCH, MS-012, SOIC-8 |
| 文件頁數(shù)： | 34/42頁 |
| 文件大?。?/td> | 954K |
| 代理商： | CY8C42123-24SXIT |
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CY8C42323/CY8C42423
PRELIMINARY
CY8C42123/CY8C42223
Document 38-12034 Rev. *C
Page 4 of 42
4.6
Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin in ports
P0 and P1. Pins can be connected to the bus individually or
in any combination. The bus also connects to the analog sys-
tem for analysis with comparators and analog-to-digital con-
verters. This bus is split into four sections, AMux Bus 0 and
AMux Bus 2, which connect to the even port pins and AMux
Bus 1 and AMux Bus 3, which connect to the odd port pins.
The four sections can be combined to support dual-channel
single-end processing, single-channel differential processing,
or dual-channel differential processing. They can also be
connected as one bus that can route to all GPIO pins.
Other multiplexer applications include:
Chip-wide mux that allows analog input from up to 10 GPIO
pins.
Crosspoint connection between any GPIO pin combina-
tions.
4.7
Additional System Resources
System Resources, some of which have been previously
listed, provide additional capability useful to complete systems
implemented in a single power block. Additional resources
include an I2C master and slave, low voltage detection, and
power on reset. Brief statements describing the merits of each
system resource are presented below.
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be
routed to both the digital and analog systems. Additional
clocks can be generated using digital PSoC blocks as clock
dividers.
The I2C module provides 50-, 100-, and 400-kHz commu-
nication over two wires. Slave, master, and multi-master
modes are all supported.
Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
4.8
Development Tools
Standard Cypress PSoC IDE tools are available for
debugging the CY8C42x23 family of parts. However, the
additional trace length and a minimal ground plane in the
Flex-Pod can create noise problems that make it difficult to
debug a Power PSoC design. A custom bonded On-Chip
Debug (OCD) device is available in an 32-pin QFN package.
The OCD device is recommended for debugging designs
that have high current and/or high analog accuracy require-
ments. The QFN package is compact and can be connected
to the ICE through a high density connector.
In-System Serial Programming (ISSP) is available.
However, ISSP for Power PSoC differs from ISSP for
standard PSoC devices. With Power PSoC devices, the
power pin (HVdd) should not be connected directly to the
Vdd pin of the ISSP connector. Doing so can damage the
programming device.
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| CY8C4245AXI-483 | 功能描述:可編程片上系統(tǒng) - PSoC RoHS:否 制造商:Cypress Semiconductor 核心:8051 處理器系列:CY8C36 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:67 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:4 KB 片上 ADC:Yes 工作電源電壓:0.5 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:QFN-68 安裝風(fēng)格:SMD/SMT |
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