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參數(shù)資料
| 型號： | CY5057 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 92K |
| 代理商： | CY5057 |
CY5057
Document #: 38-07363 Rev. *B
Page 6 of 8
AC Electrical Characteristics
[2]
Tj = –40 to 100
°
C
Timing Parameters
[2]
Parameter
F
out
tr
tf
DC
Description
Output Frequency
OUT Rise Time
OUT Fall Time
OUT Duty Cycle
Test Conditions
Min.
5
Max.
170
2.7
2.7
55
60
200
400
Unit
MHz
ns
ns
%
%
ps
ps
s
ps
ps
s
kHz
μ
W
V
DD
= 3.0 to 3.6V, C
L
= 15 pF
V
DD
= 3.0V–3.6V, 20% to 80% V
DD,
C
L
= 15 pF
V
DD
= 3.0V–3.6V, 80% to 20% V
DD,
C
L
= 15 pF
Divider output, Measured at V
DD
/2
Crystal direct output, Measured at V
DD
/2
F
out
>133 MHz, V
DD
/2, SS off
25 MHz < F
out
< 133 MHz, V
DD
/2, SS off
F
out
< 25MHz, V
DD
/2, SS off
F
out
>133 MHz, V
DD
/2, SS on
25MHz < F
out
< 133 MHz, V
DD
/2, SS on
F
out
< 25 MHz, V
DD
/2, SS on
45
40
t
J1
Peak to Peak Period
Jitter
1% of 1/F
out
200
400
1% of 1/F
out
33
540
t
J2
Cycle to Cycle Jitter
F
MOD
DL
Modulation Frequency
Crystal Drive Level
30
Measured at 25.1 MHz, with 20
R, cap setting
= hex16,
DL = 10
Measured at 25.1 MHz
–R
Negative Resistance
–140
Parameter
T
SSON1
T
SSON2
T
SSON3
T
MOD
T
STP,SYNC
T
STP,ASYNC
Time from falling edge on PD# to stopped outputs, asynchronous mode
T
PU,SYNC
Time from rising edge on PD# to outputs at valid frequency, synchronous mode
T
PU,ASYNC
Time from rising edge on PD# to outputs at valid frequency, asynchronous mode
T
PXZ,SYNC
Time from falling edge on OE to high-impedance outputs, synchronous mode, T = 1/F
out
T
PXZ,ASYNC
Time from falling edge on OE to high-impedance outputs, asynchronous mode
T
PZX,SYNC
Time from rising edge on OE to running outputs, synchronous mode, T=1/F
out
T
PZX,ASYNC
Time from rising edge on OE to running outputs, asynchronous mode
T
LOCK
PLL lock time
Description
Min.
Max.
600
100
Unit
μ
s
μ
s
μ
s
μ
s
ns
ns
ms
ms
ns
ns
ns
ns
ms
Time from steady state spread to steady state non-spread
Time from steady state non-spread to steady state spread
Minimum SSON# pulse width (positive or negative)
Spread Spectrum Modulation period
Time from falling edge on PD# to stopped outputs, synchronous mode, T = 1/F
out
250
30
33.33
1.5T + 350
350
3
3
1.5T+350
350
1.5T + 350
350
10
Switching Waveforms
Duty Cycle Timing (dc)
t
1A
t
1B
OUTPUT
Duty
t
1B
-------
100%
[
]
×
=
Output Rise/Fall Time
OUTPUT
t
r
V
DD
0V
t
f
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