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| 型號(hào)： | CY5057 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大小： | 92K |
| 代理商： | CY5057 |
CY5057
Document #: 38-07363 Rev. *B
Page 5 of 8
Absolute Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage..................................................–0.5 to +7.0V
Input Voltage............................................ –0.5V to V
DD
+ 0.5
Storage Temperature (Non-condensing).....–55
°
C to +125
°
C
Operating Conditions
Junction Temperature................................ –40
°
C to +125
°
C
Data Retention @ Tj = 125
°
C................................> 10 years
Maximum Programming Cycles........................................100
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Parameter
V
DD
T
AJ[2]
C
LC
Description
Min.
3.0
–40
Max.
3.6
100
Unit
V
°
C
Supply Voltage (3.3V)
Operating Temperature, Junction
Max. Capacitive Load on the output (CMOS levels spec)
V
DD
= 3.0V–3.6V, output frequency = 5–170 MHz
Reference Frequency with spread spectrum disabled. Fundamental
tuned crystals only.
Input Capacitance (except crystal pins)
Crystal input capacitance (all internal caps off)
Crystal output capacitance (all internal caps off)
Power-up time for all V
DD
’s to reach minimum specified voltage
(power ramps must be monotonic)
15
25.1
pF
MHz
X
REF
25.1
C
in
C
XIN
C
Xout
T
PU
7
pF
pF
pF
ms
10
10
0.05
14
14
500
DC Electrical Characteristics, Tj = –40 to 100°C
Parameter Description
V
IL
Test Conditions
CMOS levels, 30% of V
DD
V
DD
= 3.0V–3.6V
CMOS levels, 70% of V
DD
V
DD
= 3.0V–3.6V
V
DD
= 3.0V–3.6V, I
OL
= 8 mA
V
DD
= 3.0V–3.6V, I
OH
= –8 mA
Min.
Max. Unit
0.3
Input Low Voltage
PD#/OE and SSON# pins
Input High Voltage
PD#/OE and SSON# pins
Output Low Voltage, OUT pin
Output High Voltage, CMOS levels
V
DD
V
IH
0.7
V
DD
V
OL
V
OH
0.4
V
V
V
DD
–
0.4
I
ILPDOE
Input Low Current, PD#/OE pin
V
IN
= V
SS
(Internal pull-up = 3M
typical)
V
IN
= V
DD
(Internal pull-up = 100k
typical)
V
IN
= V
SS
(Internal pull-down = 100k
typical)
V
IN
= V
DD
(Internal pull-down = 100k
typical)
No Load, V
DD
= 3.0V–3.6V, Fout = 170 MHz
V
DD
= 3.0V–3.6V, Output disabled with OE
V
DD
= 3.0V–3.6V, Device powered down with PD#
V
DD
= 3.0 to 3.6V, measured at V
IN
=V
SS
V
DD
= 3.0V–3.6V, measured at V
IN
= 0.7V
DD
V
DD
= 3.0V–3.6V, measured at V
IN
= 0.5V
DD
10
μ
A
I
IHPDOE
Input High Current, PD#/OE pin
10
μ
A
I
ILSR
Input Low Current, SSON# pin
10
μ
A
I
IHSR
Input High Current, SSON# pin
50
μ
A
I
DD
I
OZ
I
PD
R
UP
Supply Current
Output Leakage Current, OUT pin
Standby Current
Pull-up Resistor on PD#/OE pin
50
50
50
6
150
150
mA
μ
A
μ
A
M
k
k
1
80
80
R
DN
Pull-down Resistor on SSON# and
OUT Pins
Crystal Feedback Resistor
Rf
V
DD
= 3.0V–3.6V, measured at X
IN
= 0.
100
k
Note:
2.
In Cypress standard TSSOP packages with external crystal.
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