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參數(shù)資料
| 型號： | CY5057 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 92K |
| 代理商： | CY5057 |
CY5057
Document #: 38-07363 Rev. *B
Page 2 of 8
Crystal Osc
with 10-bit
Cap Array
XIN
XOUT
7-bit
÷
Q
100- to
400-MHz
PLL
7-bit
Output
Divider
Block
OUT
PD#/OE
Flash Configuration/
Spread Spectrum Storage
10-bit
÷
P
Spread
Spectrum
SSON#
Die Pad Summary
Pad coordinates are referenced from the center of the die (X = 0, Y = 0).
Name
V
DD
V
SS
XIN
XOUT
PD#/OE
Die Pad
1,2
6,7
4
3
5
Description
Power supply
Ground
Crystal gate pin
Crystal drain pin
Flash-programmable to function as power down or
output enable in normal operating mode. Weak pull-up
is default enabled.
Super voltage while going into programming mode.
Data pin while going into and while in programming
mode.
Active low spread spectrum control. Asserting LOW
turns the internal modulation waveform on. Strong
pulldown is default enabled. Pulldown is disabled in
powerdown mode.
Clock pin in programming mode. Should be double
bonded to the OUT pad for pinouts not using the SSON#
function. There is an internal pull-down resistor on this
pad.
Clock output. There is an internal pull-down resistor on
this pad. Strong pulldown is default enabled. Default
output is from the reference.
No connect pin. (Do not connect this pad)
X coordinate
–843.612
883.743, 887.355
–843.612
–843.612
–843.612
Y coordinate
597.849, 427.266
–563.304, –369.957
–1.806
236.565
–424.662
V
PP
SDA
SSON#
10
834.183
589.848
SCL
OUT
9
834.183
462.840
NC
8
834.183
335.832
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