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參數(shù)資料
| 型號(hào)： | CY5057 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 92K |
| 代理商： | CY5057 |
CY5057
Document #: 38-07363 Rev. *B
Page 3 of 8
Functional Description
The CY5057 is a flash-programmable, high-accuracy,
PLL-based die designed for the crystal oscillator market. It
also contains spread spectrum circuitry that can be enabled or
disabled with an external pin. The die is integrated with a
low-cost 25.1-MHz fundamental tuned crystal in a four- or
six-pin through-hole or surface mount package. The oscillator
devices can be stocked as blank parts and custom frequencies
can be programmed in-package at the last stage before
shipping. This enables fast-turn manufacturing of custom and
standard crystal oscillators without the need for dedicated,
expensive crystals.
The CY5057 contains an on-chip oscillator and unique oscil-
lator tuning circuit for fine-tuning the output frequency. The
crystal C
load
can be selectively adjusted by programming a set
of flash memory bits. This feature can be used to compensate
for crystal variations or to obtain a more accurate synthesized
frequency.
The CY5057 uses a simple two-pin programming interface
excluding the V
SS
and V
DD
pins
.
Clock outputs can be
generated from 5 MHz to 170 MHz at 3.3V ± 10% operating
voltage. The entire Flash configuration can be reprogrammed
multiple times, allowing programmed inventory to be altered or
reused.
The CY5057 PLL die has been designed for very high
resolution. It has a 10-bit feedback counter multiplier and a
seven-bit reference counter divider. This enables the
synthesis of highly accurate and stable output clock
frequencies with zero or low PPM error. The output of the PLL
or the oscillator can be further modified by a seven-bit linear
post divider with a total of 126 divider options (2 to 127).
The CY5057 also contains flexible power management
controls. These parts include both power-down mode
(PD# = 0) and output enable mode (OE = 1). The power-down
and output enable modes have an additional setting to
determine timing (asynchronous or synchronous) with respect
to the output signal.
Controlled rise and fall times, unique output driver circuits, and
innovative circuit layout techniques enable the CY5057 to
have low jitter and accurate outputs making it suitable for most
PC, networking and consumer applications.
The CY5057 also has an additional spread spectrum feature
that can be disabled or enabled with an external pin. Please
refer to Spread Spectrum section for details.
Flash Configuration and Spread Spectrum
Storage Block
The following table summarizes the features which are config-
urable by flash memory bits. Please refer to the “CY5057
Programming Specification” for programming details. The
specification can be obtained from your Cypress factory repre-
sentative.
PLL Output Frequency
The CY5057 contains a high-resolution PLL with a 10-bit multi-
plier and a seven-bit divider.The output frequency of the PLL
is determined by the following formula:
P
BL
+
(
Q
L
+
(
where Q
L
is the loaded or programmed reference counter
value (Q counter), P
BL
is the loaded or programmed feedback
counter value (P counter), and Po is the P offset bit (can only
be 0 or 1). In Spread Spectrum mode, the time-averaged P
value is used to calculate the average frequency.
Power Management Features
The CY5057 contains Flash-programmable PD# (active LOW)
and OE (active HIGH) functions. If power-down mode is
selected (PD# = 0), the oscillator and PLL are placed in a low
supply current standby mode and the output is tri-stated and
weakly pulled low. The oscillator and PLL circuits must re-lock
when the part leaves Powerdown Mode. If output enable mode
is selected (OE = 0), the output is tri-stated and weakly pulled
low. In this mode the oscillator and PLL circuits continue to
operate, allowing a rapid return to normal operation when the
output is enabled.
In addition, the PD# and OE modes can be programmed to
occur synchronously or asynchronously with respect to the
output signal. When the asynchronous setting is used, the
powerdown or output disable occurs immediately (allowing for
logic delays) irrespective of position in the clock cycle.
However, when the synchronous setting is used, the part waits
for a falling edge at the output before powerdown or output
enable signal initiated, thus preventing output glitches. In
either asynchronous or synchronous setting, the output is
always enabled synchronously by waiting for the next falling
edge of the output.
Flash Programmable Features
Feedback counter value (P)
Reference counter value (Q)
Output divider selection
Oscillator tuning (load capacitance values)
Oscillator direct output
Power management mode (OE or PD#)
Power management timing (synchronous or asynchronous)
Spread Spectrum
Adjust
Frequency
F
PLL
4
2
)
Po
+
)
2
F
REF
=
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相關(guān)代理商/技術(shù)參數(shù) |
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| CY5057_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High-Frequency Flash Programmable PLL Die with Spread Spectrum |
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| CY5057-29WAF-IL | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High-Frequency Flash Programmable PLL Die with Spread Spectrum |
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