- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366982 > CY39200V484-125BBC (CYPRESS SEMICONDUCTOR CORP) CPLDs at FPGA Densities PDF資料下載
參數(shù)資料
| 型號： | CY39200V484-125BBC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | CPLDs at FPGA Densities |
| 中文描述： | LOADABLE PLD, 10 ns, PBGA484 |
| 封裝： | 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-484 |
| 文件頁數(shù)： | 19/86頁 |
| 文件大?。?/td> | 1212K |
| 代理商： | CY39200V484-125BBC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 19 of 86
Cluster Memory Timing Parameter Descriptions
Over the Operating Range
t
CKIN
t
IOREGPIN
PLL Parameters
t
MCCJ
t
DWSA
t
DWOSA
t
LOCK
t
INDUTY
f
PLLI
f
PLLO
f
PLLVCO
P
SAPLLI
f
MPLLI
Delay from the clock pin to the input of the clock driver
Delay from the I/O pin to the input of the I/O register
Maximum cycle to cycle jitter time
PLL zero phase delay with clock tree deskewed
PLL zero phase delay without clock tree deskewed
Lock time for the PLL
Input duty cycle
Input frequency of the PLL
Output frequency of the PLL
PLL VCO frequency of operation
Percentage modulation allowed (spread awareness) on the PLL input clock
Frequency of modulation allowed on PLL input clock. This specifies how fast the f
PLLI
sweeps between f
PLLI
*
(1–P
SAPLLI
/100) and f
PLLI
* (1+ P
SAPLLI
/100)
JTAG Parameters
t
JCKH
TCLK HIGH time
t
JCKL
TCLK LOW time
t
JCP
TCLK clock period
t
JSU
JTAG port set-up time (TDI/TMS inputs)
t
JH
JTAG port hold time (TDI/TMS inputs)
t
JCO
JTAG port clock to output time (TDO)
t
JXZ
JTAG port valid output to high impedance (TDO)
t
JZX
JTAG port high impedance to valid output (TDO)
Switching Characteristics — Parameter Descriptions
Over the Operating Range
[13]
(continued)
Parameter
Description
Parameter
Asynchronous Mode Parameters
t
CLMAA
t
CLMPWE
t
CLMSA
t
CLMHA
t
CLMSD
t
CLMHD
Synchronous Mode Parameters
t
CLMCYC1
Description
Cluster memory access time. Delay from address change to Read data out
Write Enable pulse width
Address set-up to the beginning of Write Enable with both signals from the same I/O block
Address hold after the end of Write Enable with both signals from the same I/O block
Data set-up to the end of Write Enable
Data hold after the end of Write Enable
Clock cycle time for flow through Read and Write operations (from macrocell register through cluster memory
back to a macrocell register in the same cluster)
Clock cycle time for pipelined Read and Write operations (from cluster memory input register through the
memory to cluster memory output register)
Address, data, and WE set-up time of pin inputs, relative to a global clock
Address, data, and WE hold time of pin inputs, relative to a global clock
Global clock to data valid on output pins for flow through data
Global clock to data valid on output pins for pipelined data
Cluster memory input clock to macrocell clock in the same cluster
Cluster memory output clock to macrocell clock in the same cluster
Macrocell clock to cluster memory input clock in the same cluster
t
CLMCYC2
t
CLMS
t
CLMH
t
CLMDV1
t
CLMDV2
t
CLMMACS1
t
CLMMACS2
t
MACCLMS1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY39100V484-125BBI | Photoelectric Sensor; Sensor Input Type:Optical; Sensing Range Max:60m; Sensor Output Type:Relay; Leaded Process Compatible:No; Output Type:Relay; Peak Reflow Compatible (260 C):No; Sensor Housing:Rectangular |
| CY3930Z208-125BBC | Shielded Paired Cable; Number of Conductors:2; Conductor Size AWG:22; No. Strands x Strand Size:7 x 30; Jacket Material:Polyvinylchloride (PVC); Shielding Material:Aluminum Foil/Polyester Tape; Shielding Coverage:100% RoHS Compliant: Yes |
| CY3950Z208-125BBC | CPLDs at FPGA Densities |
| CY39100Z208-125BBC | CPLDs at FPGA Densities |
| CY39200Z208-125BBC | CPLDs at FPGA Densities |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY39200V484-125BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V484-125BBXC | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Delta39K 200K 125MHz COM RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| CY39200V484-125BBXI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Delta39K 200K 125MHz IND RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| CY39200V484-125BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V484-125BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。