參數(shù)資料
型號(hào): CY39165V
英文描述: Programmable Logic
中文描述: 可編程邏輯
文件頁數(shù): 71/86頁
文件大小: 1212K
代理商: CY39165V
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 71 of 86
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
L2
L3
L4
[19]
L5
[19]
L6
[19]
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
[19]
L18
[19]
L19
[19]
L20
L21
L22
M1
M2
M3
M4
M5
M6
[19]
IO/V
REF0
NC
GCTL0
GND
GND
GND
GND
GCTL1
NC
IO/V
REF5
V
CCIO5
NC
NC
NC
NC
NC
GND
IO0
IO0
IO0
IO0
IO0
IO/V
REF0
NC
GCLK0
GND
GND
GND
GND
GCLK1
NC
IO/V
REF5
IO5
IO5
IO5
IO5
NC
GND
GND
NC
IO1
IO1
NC
IO1
IO/V
REF0
IO0
GCTL0
GND
GND
GND
GND
GCTL1
IO5
IO/V
REF5
V
CCIO5
V
CC
IO5
IO5
IO5
NC
GND
IO0
IO0
IO0
IO0
IO0
IO/V
REF0
IO0
GCLK0
GND
GND
GND
GND
GCLK1
IO5
IO/V
REF5
IO5
IO5
IO5
IO5
IO5
GND
GND
IO1
IO1
IO1
IO1
IO1
IO/V
REF0
IO0
GCTL0
GND
GND
GND
GND
GCTL1
IO5
IO/V
REF5
V
CCIO5
V
CC
IO5
IO5
IO5
IO5
GND
IO0
IO0
IO0
IO0
IO0
IO/V
REF0
IO0
GCLK0
GND
GND
GND
GND
GCLK1
IO5
IO/V
REF5
IO5
IO5
IO5
IO5
IO5
GND
GND
IO1
IO1
IO1
IO1
IO1
IO/V
REF0
IO0
GCTL0
GND
GND
GND
GND
GCTL1
IO5
IO/V
REF5
V
CCIO5
V
CC
IO5
IO5
IO5
IO5
GND
IO0
IO0
IO0
IO0
IO0
IO/V
REF0
IO0
GCLK0
GND
GND
GND
GND
GCLK1
IO5
IO/V
REF5
IO5
IO5
IO5
IO5
IO5
GND
GND
IO1
IO1
IO1
IO1
IO1
Table 14. 484 FBGA Pin Table
(continued)
Pin
CY39050
CY39100
CY39165
CY39200
相關(guān)PDF資料
PDF描述
CY39200V Programmable Logic
CY3930V208-200MGC CAP CER 1000PF 50V X7R 0805 FLEX
CY3950V208-200MGC CAP CER 10000PF 50V X7R 0805 FLX
CY39100V208-200MGC CAP CER .10UF 50V X7R 0805 FLEX
CY39165V208-200MGC CAP 100PF 50V 10% SLC SMD-0202 WAFFLE RF
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參數(shù)描述
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