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參數(shù)資料
| 型號： | CY2V9950 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 164K |
| 代理商： | CY2V9950 |
CY2V9950
Document #: 38-07436 Rev. **
Page 5 of 9
Notes:
9.
10. t
PD
is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5ns between 0.8V
–
2.0V.
11.
t
is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits.
12. Lock detector circuit may be unreliable for input frequencies lower than 4MHz, or for input signals which contain significant jitter.
Test Load = 20 pF, terminated to VCC/2. All outputs are equally loaded.
Switching Characteristics
Parameter
F
OR
VCO
LR
VCO
LBW
t
SKEWPR
Description
Condition
Min.
6
200
0.25
Max.
200
400
3.5
Unit
MHz
MHz
MHz
Output frequency range
VCO Lock Range
VCO Loop Bandwidth
Matched-Pair Skew
[9]
Skew between the earliest and the latest output
transitions within the same bank
Skew between the earliest and the latest output
transitions among all outputs
Skew between the earliest and the latest output
transitions among all same class outputs
Skew between the nominal output rising edge to the
inverted output falling edge
Skew between non-inverted outputs running at
different frequencies
Skew between nominal to inverted outputs running
at different frequencies
Skew between nominal outputs at different power
supply levels
Skew between the outputs of any two devices under
identical settings and conditions (VDDQ, VDD, temp,
air flow, frequency, etc.)
–
150
ps
t
SKEW0
Output-Output Skew
[9]
–
200
ps
t
SKEW1
–
200
ps
t
SKEW2
–
500
ps
t
SKEW3
–
500
ps
t
SKEW4
–
500
ps
t
SKEW5
–
650
ps
t
PART
Part-Part Skew
–
750
ps
t
PD0
t
ODCV
t
PWH
Ref to FB Propagation Delay
[10]
Output Duty Cycle
Output High Time Deviation
from 50%
Output Low Time Deviation
from 50%
Output Rise/Fall Time
–
250
45
+250
55
ps
%
Measured at VDD/2
Measured at 2.0V for VDD = 3.3V and at 1.7V for
VDD = 2.5V.
Measured at 0.8V for VDD = 3.3V and at 0.7V for
VDD = 2.5V.
Measured at 0.8V
–
2.0V for VDD = 3.3V and 0.7V
–
1.7V for VDD = 2.5V
–
1.5
ns
t
PWL
–
2.0
ns
t
R
/t
F
0.15
1.5
ns
t
LOCK
t
CCJ
PLL lock time
[11,12]
Cycle-Cycle Jitter
–
0.5
ms
Divide by 1 output frequency, FS = L, FB = divide
by 1, 2, 4
Divide by 1 output frequency, FS = M/H, FB = divide
by 1, 2, 4
–
100
ps
–
150
ps
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PDF描述 |
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| CY545B | Stepper Motor Controller/Driver |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY2V9950AC | 制造商:Rochester Electronics LLC 功能描述:2.5/3.3V 200 MHZ LVCMOS INPUT, 8 OUTPUT ZDB - Bulk |
| CY2V9950ACT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
| CY2V9950AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
| CY2V9950AIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
| CY2V995AC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:S2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer |
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